NT256D64S88B1GY datasheet(7/28 Pages) ETC1

Part #	NT256D64S88B1GY

Description	184 pin Unbuffered DDR DIMM

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NT512D64S8HB1G / NT512D64S8HB1GY / NT512D64S8HB0G

NT256D64S88B1G / NT256D64S88B1GY NT256D64S88B0G

NT128D64SH4B1G / NT512D72S8PB0G (ECC) / NT256D72S89B0G (ECC)

Unbuffered DDR DIMM

REV 2.2

7

Aug 3, 2004

Preliminary

NANYA reserves the right to change products and specifications without notice.

Functional Block Diagram

1 Rank, 4 devices, 16Mx16 DDR SDRAMs

Serial PD

A0

A2

A1

SCL

WP

SDA

SA0

SA2

SA1

A0-A13

RAS

BA0-BA1

BA0-BA1 : SDRAMs D0-D3

A0-A13 : SDRAMs D0-D3

RAS : SDRAMs D0-D3

CKE0

CAS

CAS : SDRAMs D0-D3

CKE : SDRAMs D0-D3

WE

WE : SDRAMs D0-D3

V

DDSPD

V

SS

V

REF

V

DDID

V

DD/VDDQ

Strap: see Note 4

SPD

D0-D3

* Wire per Clock Loading Table/

Wiring Diagrams

* Clock Wiring

Clock Input

SDRAMs

*CK0/

CK0

*CK1/

CK1

*CK2/

CK2

NC

2 SDRAMs

S0

DM1/DQS10

DQ8

DQ9

DQ10

DQ15

DQ12

DQ14

DQ13

DQ11

DQ0

DQ1

DQ2

DQ7

DQ4

DQ6

DQ5

DQ3

DQ24

DQ25

DQ26

DQ31

DQ28

DQ30

DQ29

DQ27

DQ16

DQ17

DQ18

DQ23

DQ20

DQ22

DQ21

DQ19

DQS1

DM5/DQS14

DQS5

DM0/DQS9

DQS0

DM3/DQS12

DQS3

DM2/DQS11

DQS2

DQ40

DQ41

DQ42

DQ47

DQ44

DQ46

DQ45

DQ43

DQ32

DQ33

DQ34

DQ39

DQ36

DQ38

DQ37

DQ35

DQS4

DM4/DQS13

DQ56

DQ57

DQ58

DQ63

DQ60

DQ62

DQ61

DQ59

DQ48

DQ49

DQ50

DQ55

DQ52

DQ54

DQ53

DQ51

DQS7

DM7/DQS16

DQS6

DM6/DQS15

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

CS

D0

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

CS

D2

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

CS

D3

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

I/O 6

I/O 4

I/O 5

I/O 0

I/O 2

I/O 3

I/O 1

I/O 7

LDM

CS

D1

I/O 8

I/O 10

I/O 11

I/O 14

I/O 12

I/O 13

I/O 15

I/O 9

UDM

UDQS

LDQS

Notes :

1. DQ-to-I/O wiring is shown as recommended but may be changed.

2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.

3. DQ, DQS, DM/DQS resistors: 22 Ohms.

4. V

DDID strap connections (for memory device VDD, VDDQ):

STRAP OUT (OPEN): V

DD = VDDQ

STRAP IN (V

SS): VDD is not equal to VDDQ.

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