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HD6417750RF200 Datasheet(PDF) 9 Page - Renesas Technology Corp |
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HD6417750RF200 Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 1039 page Rev. 6.0, 07/02, page vii of I Section Page Item Description 5.6.3 Interrupts 157 (3) Peripheral Module Interrupts Description changed 7.3 Instruction Set 186 Table 7.7 Branch Instructions Description added 8.3 Execution Cycles and Pipeline Stalling 204 to 206 Description amended Note changed 9.1.1 Types of Power-Down Modes 222 Table 9.1 Status of CPU and Peripheral Modules in Power- Down Modes Hardware standby (SH7750S, SH7750R) added to table, description amended 9.1.2 Register Configuration 223 Table 9.2 Power-Down Mode Registers Description and Note added to table 9.1.3 Pin Configuration 223 Table 9.3 Power-Down Mode Pins Description added to Function in table and amended 9.2.2 Peripheral Module Pin High Impedance Control 226 Other information Description amended 9.2.3 Peripheral Module Pin Pull-Up Control 226 Other Information Added 9.2.4 Standby Control Register 2 (STBCR2) 227 Bit table Bit 6 amended to STHZ and bit 1 to MSTP6, note added 227 Bit 6, Bits 1 and 0 Description added 9.2.5 Clock-Stop Register 00 (CLKSTP00) (SH7750R Only) 228, 229 Newly added 9.2.6 Clock-Stop Clear Register 00 (CLKSTPCLR00) (SH7750R Only) 229 Added 9.4.1 Transition to Deep Sleep Mode 230 Description amended, Note added 9.5.2 Exit from Standby Mode 232 Exit by Interrupt Note added 9.6.1 Transition to Module Standby Function 234 Text amended Table description and note added 9.6.2 Exit from Module Standby Function 234 Description amended Note deleted 9.7 Hardware Standby Mode (SH7750S, SH7750R Only) 235 SH7750R added |
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