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HD6417750SF200 Datasheet(PDF) 7 Page - Renesas Technology Corp |
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HD6417750SF200 Datasheet(HTML) 7 Page - Renesas Technology Corp |
7 / 1039 page Rev. 6.0, 07/02, page v of I List of Items Revised or Added for This Version Section Page Item Description 1.1 SH7750 Series (SH7750, SH7750S, SH7750R) Features 1 Description amended and added 4 to 8 Table 1.1 SH7750 Series Features Description added for LSI, and description and Note added for Clock pulse generator (CPG) SH7750 and SH7750S added to cache memory Cache memory [SH7750R] added to table Description added for Direct memory access controller (DMAC) and Timer unit (TMU) SH7750R table added to Product lineup Notes 1, 2, 3 added 1.2 Block Diagram 9 Figure 1.1 Block Diagram of SH7750 Series Functions I cache 8 KB and 0 cache 16 KB deleted from table 1.3 Pin Arrangement 10 to 12 Figure 1.2 to 1.4 SH7750R added, and description amended 1.4 Pin Functions 13 to 40 Table 1.2 to 1.4 Table and note amended 2.7 Processor Modes 55 Description deleted 3.2 Register Descriptions 61 Figure 3.2 MMU-Related Registers Amended 62 3. Page table entry assistance register (PTEA) SH7750R added after SH7750S 62 1. Page table entry high register (PTEH), 6. MMU control register (MMUCR) Description added 3.3.1 Physical Address Space 64 to 67 Description added |
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Similar Description - HD6417750SF200 |
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