Electronic Components Datasheet Search |
|
OR3T30-6BA256I Datasheet(PDF) 8 Page - Agere Systems |
|
OR3T30-6BA256I Datasheet(HTML) 8 Page - Agere Systems |
8 / 210 page 8 8 Lucent Technologies Inc. Data Sheet June 1999 ORCA Series 3C and 3T FPGAs Description (continued) PIC Logic Series 3 PIC addresses the demand for ever-increas- ing system clock speeds. Each PIC contains four pro- grammable inputs/outputs (PIOs) and routing resources. On the input side, each PIO contains a fast- capture latch that is clocked by an ExpressCLK. This latch is followed by a latch/FF that is clocked by a sys- tem clock from the internal general clock routing. The combination provides for very low setup requirements and zero hold times for signals coming on-chip. It may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer. Two input signals are available to the PLC array from each PIO, and the ORCA 2C/2T capability to use any input pin as a clock or other global input is maintained. On the output side of each PIO, two outputs from the PLC array can be routed to each output flip-flop, and logic can be associated with each I/O pad. The output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. The output FF in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. The I/O buffer associated with each pad is very similar to the ORCA 2C/2T Series buffer with a new, fast, open-drain option for ease of use on system buses. System Features Series 3 also provides system-level functionality by means of its dual-use microprocessor interface and its innovative programmable clock manager. These func- tional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today’s high-speed systems. Routing The abundant routing resources of the ORCA Series 3 FPGAs are organized to route signals individually or as buses with related control signals. Clocks are routed on a low-skew, high-speed distribution network and may be sourced from PLC logic, externally from any I/O pad, or from the very fast ExpressCLK pins. Express- CLKs may be glitchlessly and independently enabled and disabled with a programmable control signal using the new StopCLK feature. The improved PIC routing resources are now similar to the patented intra-PLC routing resources and provide great flexibility in moving signals to and from the PIOs. This flexibility translates into an improved capability to route designs at the required speeds when the I/O signals have been locked to specific pins. Configuration The FPGA’s functionality is determined by internal configuration RAM. The FPGA’s internal initialization/ configuration circuitry loads the configuration data at powerup or under system control. The RAM is loaded by using one of several configuration modes. The con- figuration data resides externally in an EEPROM or any other storage media. Serial EEPROMs provide a sim- ple, low pin count method for configuring FPGAs. A new, easy method for configuring the devices is through the microprocessor interface. |
Similar Part No. - OR3T30-6BA256I |
|
Similar Description - OR3T30-6BA256I |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |