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AD9216-65 Datasheet(PDF) 4 Page - Analog Devices |
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AD9216-65 Datasheet(HTML) 4 Page - Analog Devices |
4 / 20 page AD9216 Preliminary Technical Data Rev. PrD Page 4 of 20 6/15/2004 DC SPECIFICATIONS (CONTINUED) Table 2. (AVDD = 3 V, DRVDD = 2.5 V, Maximum Sample Rate, CLK_A = CLK_B; AIN = -0.5 dBFS Differential Input, 1.0 V Internal Reference, TMIN to TMAX, unless otherwise noted.) Test AD9216BCP-65/80 AD9216BCP-105 Unit Parame ter Temp Level Min Typ Max Min Typ Max LOGIC INPUTS High Level Input Voltage Full IV 2.0 2.0 V Low Level Input Voltage Full IV 0.8 0.8 V High Level Input Current Full IV - 10 +10 - 10 +10 µA Low Level Input Current Full IV - 10 +10 - 10 +10 µA Input Capacitance Full IV 2 2 pF LOGIC OUTPUTS 1 DRVDD = 2.5V High Level Output Voltage Full IV 2.45 2.45 V Low Level Output Voltage Full IV 0.05 0.05 V 1 Output Voltage Levels measured with 5 pF load on each output. Specifications subject to change without notice. SWITCHING SPECIFICATIONS Table 3. Switching Specifications Test AD9216BCP-65/80 AD9216BCP-105 Parameter Temp Level Min Typ Max Min Typ Max Unit SWITCHING PERFORMANCE Max Conversion Rate Full VI 65/80 105 MSPS Min Conversion Rate Full V 1 1 MSPS CLK Period Full V 15.4/12.2 9.5 ns CLK Pulsewidth High 1 Full V 6.2/5 4.2 ns CLK Pulsewidth Low 1 Full V 6.2/5 4.2 ns DATA OUTPUT PARAMETER Output Delay 2 (t PD) Full VI 2.0 4.8 6.0 2.0 4.8 6.0 ns Pipeline Delay (Latency) Full V 6 6 Cycles Aperture Delay (tA) Full V 1.0 1.0 ns Aperture Uncertainty (tJ) Full V 0.5 0.5 ps rms Wake-Up Time 3 Full V 2.5 2.5 ms OUT-OF-RANGE RECOVERY TIME Full V 2 2 1 The AD9216 has a duty cycle stabilizer circuit that, when enabled, corrects for a wide range of duty cycles (see TPC xx). 2 Output delay is measured from CLOCK 50% transition to DATA 50% transition, with a 5 pF load on each output. 3 Wake-up time is dependent on the value of the decoupling capacitors; typical values shown with 0.1 µF and 10 µF capacitors on REFT and REFB. Specifications subject to change without notice. t A t PD N–8 N–7 N–6 N–5 N–4 N–3 N–2 N-1 N N+1 ANALOG INPUT CLK DATA OUT N–1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 Figure 2. Timing Diagram |
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