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TR3005 Datasheet(PDF) 5 Page - RF Monolithics, Inc |
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TR3005 Datasheet(HTML) 5 Page - RF Monolithics, Inc |
5 / 12 page 5 the start of the next RFA1 ON sequence should be set to sample the narrowest RF data pulse at least 10 times. Otherwise, significant edge jitter will be added to the detected data pulse. ASH Transceiver Block Diagram Figure 2 is the general block diagram of the ASH transceiver. Please refer to Figure 2 for the following discussions. Antenna Port The only external RF components needed for the transceiver are the antenna and its matching components. Antennas presenting an impedance in the range of 35 to 72 ohms resistive can be satisfacto- rily matched to the RFIO pin with a series matching coil and a shunt matching/ESD protection coil. Other antenna impedances can be matched using two or three components. For some impedances, two inductors and a capacitor will be required. A DC path from RFIO to ground is required for ESD protection. Receiver Chain The output of the SAW filter drives amplifier RFA1. This amplifier in- cludes provisions for detecting the onset of saturation (AGC Set), and for switching between 35 dB of gain and 5 dB of gain (Gain Se- lect). AGC Set is an input to the AGC Control function, and Gain Se- lect is the AGC Control function output. ON/OFF control to RFA1 (and RFA2) is generated by the Pulse Generator & RF Amp Bias function. The output of RFA1 drives the SAW delay line, which has a nominal delay of 0.5 µs. The second amplifier, RFA2, provides 51 dB of gain below satura- tion. The output of RFA2 drives a full-wave detector with 19 dB of threshold gain. The onset of saturation in each section of RFA2 is detected and summed to provide a logarithmic response. This is added to the output of the full-wave detector to produce an overall detector response that is square law for low signal levels, and tran- sitions into a log response for high signal levels. This combination provides excellent threshold sensitivity and more than 70 dB of detector dynamic range. In combination with the 30 dB of AGC range in RFA1, more than 100 dB of receiver dynamic range is achieved. The detector output drives a gyrator filter. The filter provides a three-pole, 0.05 degree equiripple low-pass response with excellent group delay flatness and minimal pulse ringing. The 3 dB bandwidth of the filter can be set from 4.5 kHz to 1.8 MHz with an external re- sistor. The filter is followed by a base-band amplifier which boosts the de- tected signal to the BBOUT pin. When the receiver RF amplifiers are operating at a 50%-50% duty cycle, the BBOUT signal changes about 10 mV/dB, with a peak-to-peak signal level of up to 685 mV. For lower duty cycles, the mV/dB slope and peak-to-peak signal level are proportionately less. The detected signal is riding on a 1.1 Vdc level that varies somewhat with supply voltage, tempera- ture, etc. BBOUT is coupled to the CMPIN pin or to an external data recovery process (DSP, etc.) by a series capacitor. The correct value of the series capacitor depends on data rate, data run length, and other factors as discussed in the ASH Transceiver Designer’s Guide. When an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery process and CMPIN by separate series coupling capacitors. The AGC reset function is driven by the signal applied to CMPIN. When the transceiver is placed in power-down (sleep) or in a trans- mit mode, the output impedance of BBOUT becomes very high. This feature helps preserve the charge on the coupling capacitor to mini- mize data slicer stabilization time when the transceiver switches back to the receive mode. Data Slicers The CMPIN pin drives two data slicers, which convert the analog signal from BBOUT back into a digital stream. The best data slicer choice depends on the system operating parameters. Data slicer DS1 is a capacitively-coupled comparator with provisions for an ad- justable threshold. DS1 provides the best performance at low ASH Transceiver Block Diagram RFA1 RFA2 TXA1 TXA2 SAW Delay Line SAW CR Filter Log Antenna RFIO Tuning/ESD Detector Low-Pass Filter BB AGC Control Peak Detector Pulse Generator & RF Amp Bias LPFADJ PRATE PWIDTH RXDATA TXMOD CN TRL1 CN TRL0 AGCCAP R REF THLD2 THLD1 Modulation & Bias Control Power Down Control Gain Select AGC Set AGC Reset Threshold Control BBOUT DS2 DS1 AND dB Below Peak Thld Ref Thld PKDET Ref AGC C BBO C PKD R LPF C AGC R PR R PW R TH2 R TH1 R TXM 20 8 17 18 14 15 3 9 5 6 4 7 13 11 12 VCC1: Pin 2 VCC2: Pin 16 GND1: Pin 1 GND2: Pin 10 GND3: Pin 19 RREF: Pin 11 CMPIN: Pin 6 TX IN Tuning Figure 2 |
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