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MPC962308D-4R2 Datasheet(PDF) 6 Page - Motorola, Inc |
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MPC962308D-4R2 Datasheet(HTML) 6 Page - Motorola, Inc |
6 / 12 page MPC962308 TIMING SOLUTIONS 6 MOTOROLA APPLICATIONS INFORMATION Figure 1. Output-to-Output Skew tSK(O) Figure 2. Static Phase Offset Test Reference Figure 3. Output Duty Cycle (DC) VCC VCC ÷ 2 GND VCC VCC ÷ 2 GND t6 CCLK FB_IN The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device VCC 1.4 V GND VCC 1.4 V GND t5 The time from the PLL controlled edge to the non-controlled edge, divided by the time between PLL controlled edges, expressed as a percentage VCC 1.4 V GND t2 t1 DC = t2/t1 x 100% Figure 5. Cycle-to-Cycle Jitter t4 t3 VCC = 3.3 V 2.0 0.8 Figure 6. Output Transition Time Test Reference The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs tN tJ = |tN–tN+1| tN+1 Figure 4. Device-to-Device Skew VCC VCC ÷ 2 GND VCC VCC ÷ 2 GND t7 DEVICE 1 DEVICE 2 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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