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(SDT8028-T_-Q_)
Specification : TS-S96D048F
July, 2001
5. Absolute Maximum Ratings
6. Electrical Interface
( Unless otherwise specified, Vcc-Vee = 4.75 to 5.25 V @2488.32Mbps, PRBS2^23-1, 50% duty
and all operating temperature shall apply.)
Warning
Use the product with the rated voltage described in the specification. If the voltage exceeds the maximum rating, overheating or fire
may occur.
Caution
Do not store the product in the area where temperature exceeds the maximum rating, where there is too much moisture or damp-
ness, where there is acid gas or corrosive gas, or other extreme conditions. Otherwise, failure, overheating or fire may occur.
1. Termination current is not included. 2. Measured between each signal input and VTTD or VTTC. Refer to Figure 3.
3. Refer to Figure 4. 4. Default (Open) normal operation. 5. Default (Open) clocked mode. 6. Alarm will be launched when LD bias
current exceeds 70mA typ. 7. LD bias current can be monitored by measuring the voltage difference between BM(+) Pin 22 and BM(-) Pin
21. Please refer to Figure 5.
8. Rear Facet PD current can be monitored by measuring the voltage difference between RFM(+) Pin 3 and
RFM(-) Pin 4. Please refer to Figure 5. 9. High input impedance ( > 1M
Ω) device is required to measure this voltage.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Note
Supply Voltage
Vcc-Vee
4.75
5.00
5.25
V
Supply Current
Id
150
200
mA
1
Input Impedance ( Data and Clock)
Rin
50
Ω
2
Input VoltageHighVIH
Vcc-1.00
Vcc-0.90
Vcc-0.70
V
(Data and Clock, for ECL or PECL interface)
Low
VIL
Vcc-1.90
Vcc-1.70
Vcc-1.60
V
Differential Input Voltage Swing for AC coupled interface
Vin
0.45
0.80
1.20
Vp-p
Input Signal Rise Time (20% - 80%)
Tr
100
120
ps
Input Signal Fall Time (20% - 80%)
Tf
100
120
ps
Setup Time (for clocked mode)
Tset
130
ps3
Hold Time (for clocked mode)
Thold
75
ps3
Disable Input Voltage
Disable
Vdisbl
Vee+2.00
Vcc
V
4
Enable
Venbl
Vee
Vee+0.8
V
Selector Input Voltage
Clocked
Vslct
Vee
Vee+1.5
V
5
Non Clocked
Vnclct
Vcc-1.5
Vcc
V
LD Bias Alarm Output Voltage
Normal
Valml
Vee
Vee+0.5
V
6
Abnormal
Valmh
Vcc-1.00
Vcc
V
LD Bias Monitor Voltage (between pin 22 and pin 21)
Vbm
0.01
0.10
0.50
V
7, 9
Rear Facet PD monitor Voltage (between pin 3 and pin 4)
Vrfm
0.01
0.10
0.25
V
8, 9
Parameter
Symbol
min.
Max
Unit
Note
Storage Case Temperature
Ts
-40
85
°C
1
Operating Case Temperature
TC
070
°C
1
Supply Voltage
Vcc-Vee
0.0
6.0
V
2
Input VoltageVi
Vee
Vcc
V
3
Lead Soldering (Temperature)
260
°C
4
(Time)
10
sec.
Note 1. No condensation allowed. 2. Vcc>Vee, Vcc=+5.0V for Vee=GND or Vcc=GND for Vee=-5.0V
3. Data, Clock, Disable and Selector 4. Measured on lead pins 2mm (0.079in.) off the package bottom
Rin
Rin
10k
Ω
Rin
Rin
V ref = V c c - 1.4V ty p.
TD
V TTD
TC L K
V TTC
10k
Ω
10k
Ω
10k
Ω
Vre f
Vre f
TD b
TC L K b
Figure 3. Data and Clock Input Interface
T = 400 ps ec
TD
TC L K
T s et
T hold
TD b
TC L K b
Figure 4. Input Data and Clock Timing
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