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IDTCSPT857CNL Datasheet(PDF) 7 Page - Integrated Device Technology |
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IDTCSPT857CNL Datasheet(HTML) 7 Page - Integrated Device Technology |
7 / 15 page 7 IDTCSPT857C 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIALANDINDUSTRIALTEMPERATURERANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200 FollowingConditionsApplyUnlessOtherwiseSpecified: Commercial: TA = 0°C to +70°C; Industrial: TA = -40°C to +85°C Symbol Parameter Conditions Min. Typ. Max. Unit VIK InputClampVoltage(AllInputs) VDDQ = 2.5V, II = -18mA – 1.2 V VIL(dc) StaticInputLOWVoltage PWRDWN – 0.3 0.7 V VIH(dc) Static Input HIGH Voltage PWRDWN 1.7 VDDQ + 0.3 VIL(ac) DynamicInputLOWVoltage CLK, CLK, FBIN, FBIN 0.7 V VIH(ac) Dynamic Input HIGH Voltage CLK, CLK, FBIN, FBIN 1.7 VDDQ VOL OutputLOWVoltage AVDD/VDDQ = Min., IOL = 100 µA 0.1 V AVDD/VDDQ = Min., IOL = 12mA 0.6 VOH Output HIGH Voltage AVDD/VDDQ = Min., IOH = -100 µAVDDQ – 0.1 V AVDD/VDDQ = Min., IOH = -12mA 1.7 VIX InputDifferentialCrossVoltage VDDQ/2 – 0.2 VDDQ/2 + 0.2 V VID(DC)(1) DCInputDifferentialVoltage 0.36 VDDQ + 0.6 V VID(AC)(1) ACInputDifferentialVoltage 0.7 VDDQ + 0.6 V IIN InputCurrent VDDQ = 2.7V, VI = 0V to 2.7V ±10 µA IDDPD Power-Down Current on VDDQ and AVDD AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L 100 200 µA IDDQ Dynamic Power Supply Current on VDDQ AVDD/VDDQ = Max., CLK = 200MHz, 120 Ω/14pF 320 360 mA AVDD/VDDQ = Max., CLK = 200MHz, 120 Ω/14pF 250 300 IADD Dynamic Power Supply Current on AVDD AVDD/VDDQ = Max., CLK = 200MHz 12 mA NOTE: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK. TIMING REQUIREMENTS FOR PC3200 Symbol Parameter Min. Max. Unit fCLK OperatingClockFrequency(1,2) 60 220 MHz ApplicationClockFrequency(1,3) 60 220 MHz tDC Input Clock Duty Cycle 40 60 % tL StabilizationTime(4) 100 µs NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. TIMING REQUIREMENTS FOR PC1600 - PC2700 Symbol Parameter Min. Max. Unit fCLK OperatingClockFrequency(1,2) 60 200 MHz ApplicationClockFrequency(1,3) 60 200 MHz tDC Input Clock Duty Cycle 40 60 % tL StabilizationTime(4) 100 µs NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. |
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