In-Path vs. Parallel Fail-Safe

The MAX9171/MAX9172 have in-path fail-safe that is

compatible with in-path fail-safe receivers, such as the

DS90LV018A and DS90LV028A. Refer to the MAX9111/

MAX9113 data sheet for pin-compatible receivers with

parallel fail-safe and lower jitter. Refer to the MAX9130

data sheet for a single LVDS receiver with parallel fail-

safe in an SC70 package.

The MAX9171/MAX9172 with in-path fail-safe are

designed with a +40mV input offset voltage, a 2.5µA

input, and a 5µA current sink between the inverting

input and ground (Figure 1). If the differential input is

0.7V and the 5µA source sink pulls the inverting input to

ground, which drives the receiver output high. If the dif-

ferential input is shorted or terminated with a typical

value termination resistor, the +40mV offset drives the

receiver output high. If the input is terminated and float-

ing, the receiver output is driven high by the +40mV off-

set, and the 2:1 current sink to current source ratio

(5µA:2.5µA) pulls the inputs to ground. This can be an

advantage when switching between drivers on a multi-

point bus because the change in common-mode volt-

age from ground to the typical driver offset voltage of

the propagation delay and transition test time circuit

and Figure 3 shows the propagation delay and transi-

tion test time waveforms.

Single/Dual LVDS Line Receivers with

“In-Path” Fail-Safe

_______________________________________________________________________________________

7

OUT_

IN_+

IN_-

5

µA

2.5

µA

40mV

Figure 1. Input with In-Path Fail-Safe Network Equivalent Circuit

50

Ω

50

Ω

IN_-

OUT_

IN_+

15pF

PULSE

GENERATOR

Figure 2. Propagation Delay and Transition Test Time Circuit

IN_+

IN_-

20%

80%

OUT_

1.5V

1.5V

20%

80%

1.2V (0V DIFFERENTIAL)

1.3V

1.1V

Figure 3. Propagation Delay and Transition Time Waveforms