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W83194BR-648 Datasheet(PDF) 11 Page - Winbond |
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W83194BR-648 Datasheet(HTML) 11 Page - Winbond |
11 / 26 page W83194BR-648 Publication Release Date: April 13, 2005 - 7 - Revision 1.1 7. I 2C CONTROL AND STATUS REGISTERS The Register 0~3 are reserved for external clock buffer (The register No. Is increased by 1 if use byte data read/write protocol) 7.1 Register 4: Frequency Select (Default = 00H) BIT NAME PWD DESCRIPTION 7 SSEL [3] 0 6 SSEL [2] 0 5 SSEL [1] 0 4 SSEL [0] 0 Frequency selection by software via I2C 3 EN_SSEL 0 Enable software program FS [4:0]. 0 = Select frequency by hardware. 1 = Select frequency by software I2C - Bit 4:7, 2. 2 SSEL [4] 0 Frequency selection bit 4 1 EN_SPSP 0 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled 0 EN_SAFE_FREQ 0 Enable reload safe frequency when the watchdog is timeout. 0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 9 bit 4~0. 7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH) BIT PIN NO PWD DESCRIPTION 7 47 1 SDRAM output control 6 44, 43 1 CPUCLKT/C1 output control 5 40, 39 1 CPUCLKT/C0 output control 4 15 X Invert Power on latched value of FS4 pin, Default 1 (Read only) 3 14 X Invert Power on latched value of FS3 pin. Default 1 (Read only) 2 4 X Invert Power on latched value of FS2 pin. Default 1 (Read only) 1 3 X Invert Power on latched value of FS1 pin. Default 1 (Read only) 0 2 X Invert Power on latched value of FS0 pin. Default 1 (Read only) |
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