W83176R-735

Publication Release Date: April 13, 2005

- 1 -

Revision 1.1

1. GENERAL DESCRIPTION

The W83176R-735 is a 2.5V Zero-delay D.D.R. Clock buffer designed for SiS system. W83176R-735

can support 3 D.D.R. DRAM DIMMs.

clock outputs. The W83176R-735 accepts a reference clock as its input and runs on 2.5V supply.

2. FEATURES

• Zero-delay clock outputs

• Feedback pins for synchronous

• Supports up to 3 D.D.R. DIMMs

• One pairs of additional outputs for feedback

•

Low Skew outputs (<100 pS)

•

Supports 400 MHz D.D.R. SDRAM

• Packaged in 48-pin SSOP

3. PIN CONFIGURATION

GN D 1

48 GN D

CLK C 0 2

47 CLKC5

C LKT0 3

46 CLKT5

VD D 4

45 VD D

C LKT1 5

44 CLKT6

CLK C 1 6

43 CLKC6

GN D 7

42 GN D

GN D 8

41 GN D

CLK C 2 9

40 CLKC7

C LK T210

39C LK T7

VD D 11

38 V D D

* S C LK 12

37 S D A TA *

C LK _IN T 13

36 N /C

N/C 14

35 FB_IN T

VD D 15

34 V D D

A V D D 16

33 FB _O U TT

A G N D 17

32 N C

GN D 18

31 G N D

C LK C 319

30C LK C 8

C LK T320

29C LK T8

VD D 21

28 V D D

C LK T422

27C LK T9

C LK C 423

26C LK C 9

GN D 24

25 G N D

*: Internal pull-up resistor 120K to VDD