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SN65HVD1050R Datasheet(PDF) 4 Page - Texas Instruments |
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SN65HVD1050R Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 19 page  www.ti.com DRIVER SWITCHING CHARACTERISTICS RECEIVER ELECTRICAL CHARACTERISTICS SN65HVD1050 SLLS632 – DECEMBER 2005 DRIVER ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditiions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VI = 0 V, RL = 60 Ω, S at 0 V, See Figure 1, 1.5 3 V Figure 2, and Figure 3 VOD(D) Differential output voltage (Dominant) VI = 0 V, RL = 45 Ω, S at 0 V, See Figure 1, 1.4 3 V Figure 2, and Figure 3 VI = 3 V, S at 0 V, See Figure 1 and Figure 2 –0.012 0.012 VOD(R) Differential output voltage (Recessive) V VI = 3 V, S at 0 V, No Load –0.5 0.05 Steady state common-mode output VOC(ss) 2 2.3 3 V voltage S at 0 V, Figure 8 Change in steady-state common-mode ∆V OC(ss) 30 mV output voltage IIH High-level input current, TXD input VI at VCC –2 2 IIL Low-level input current, TXD input VI at 0 V –50 –10 µA IO(off) Power-off TXD output current VCC at 0 V, TXD at 5 V 1 VCANH = -12 V, CANL Open, See Figure 11 –105 –72 VCANH = 12 V, CANL Open, SeeFigure 11 0.36 1 IOS(ss) Short-circuit steady-state output current mA VCANL = -12 V, CANH Open, See Figure 11 –1 –0.5 VCANL = 12 V, CANH Open, See Figure 11 71 105 CO Output capacitance See receiver input capacitance over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay time, low-to-high-level output 25 65 120 tPHL Propagation delay time, high-to-low-level output 25 45 90 S at 0 V, See Figure 4 ns tr Differential output signal rise time 25 tf Differential output signal fall time 50 ten Enable time from silent mode to dominant See Figure 7 1 µs t(dom) Dominant time-out ↓V I, See Figure 10 300 450 700 µs over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT VIT+ Positive-going input threshold voltage 800 900 S at 0 V, See Table 1 VIT– Negative-going input threshold voltage 500 650 mV Vhys Hysteresis voltage (VIT+– VIT–) 100 125 VOH High-level output voltage IO = –2 mA, See Figure 6 4 4.6 V VOL Low-level output voltage IO = 2 mA, See Figure 6 0.2 0.4 V CANH or CANL = 5 V, II(off) Power-off bus input current Other pin at 0 V, 165 250 µA VCC at 0 V, TXD at 0 V IO(off) Power-off RXD leakage current VCC at 0 V, RXD at 5 V 20 µA TXD at 3 V, CI Input capacitance to ground, (CANH or CANL) 13 VI = 0.4 sin (4E6πt) + 2.5 V pF CID Differential input capacitance TXD at 3 V, VI = 0.4 sin (4E6πt) 5 RID Differential input resistance 30 80 TXD at 3 V, S at 0 V k Ω RIN Input resistance, (CANH or CANL) 15 30 40 (1) All typical values are at 25°C with a 5-V supply. 4 |
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