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56F8347 Datasheet(PDF) 7 Page - Freescale Semiconductor, Inc |
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56F8347 Datasheet(HTML) 7 Page - Freescale Semiconductor, Inc |
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7 / 176 page  Device Description 56F8347 Technical Data, Rev. 3.0 Freescale Semiconductor 7 Preliminary • Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines) • Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional GPIO lines) — In the 56F8347, SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B — In the 56F8147, SPI1 can alternately be used only as GPIO • Computer Operating Properly (COP) / Watchdog timer • Two dedicated external interrupt pins • Up to 76 General Purpose I/O (GPIO) pins • External reset input pin for hardware reset • External reset output pin for system reset • JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent, real-time debugging • Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock 1.1.5 Energy Information • Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs • On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be disabled • On-chip regulators for digital and analog circuitry to lower cost and reduce noise • Wait and Stop modes available • ADC smart power management • Each peripheral can be individually disabled to save power 1.2 Device Description The 56F8347 and 56F8147 are members of the 56800E core-based family of hybrid controllers. Each combines, on a single chip, the processing power of a Digital Signal Processor (DSP) and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F8347 and 56F8147 are well-suited for many applications. The device includes many peripherals that are especially useful for motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control (56F8347 only), engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation applications. The 56800E core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F8347 and 56F8147 support program execution from internal or external memories. Two data operands can be accessed from the on-chip data RAM per instruction cycle. These devices also provide two external dedicated interrupt lines and up to 76 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. |
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