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PLL

TA0−TA6

OUT

IN

TA+

TA−

7

TB+

TB−

TCLK+

TCLK−

CLK IN

>CLK

OUT

IN

TB0−TB6

7

R/F

TX ENABLE

PLL

CLK<

OUT

IN

RA0−RA6

7

RA+

RA−

RB0−RB6

7

RB+

RB−

RCLK+

RCLK−

CLK OUT

OUT

IN

RX ENABLE

100 ~

100 ~

100 ~

Parallel In

to

Serial Out

Serial In

to

Parallel Out

SN75LVDT1422

SLLS653 – JUNE 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device

placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

FUNCTIONAL BLOCK DIAGRAM

2