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RECEIVER SWITCHING CHARACTERISTICS

SN75LVDT1422

SLLS653 – JUNE 2005

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CLK OUT

1.2

2.5

CMOS/LVTTL Rise time

See Figure 3

ns

RA or RB

2.0

3.5

CLK OUT

1.2

2.5

CMOS/LVTTL Fall time

See Figure 3

ns

RA or RB

2.0

3.5

Input strobe position for bit 0

0.45

0.84

1.23

Input strobe position for bit 1

2.13

2.52

2.91

Input strobe position for bit 2

3.81

4.20

4.59

Input strobe position for bit 3

f = 85 MHz, See Figure 17

5.49

5.88

6.27

ns

Input strobe position for bit 4

7.17

7.56

7.95

Input strobe position for bit 5

8.85

9.24

9.63

Input strobe position for bit 6

10.53

10.92

11.31

Input strobe position for bit 0

0.40

0.71

1.02

Input strobe position for bit 1

1.83

2.14

2.45

Input strobe position for bit 2

3.26

3.57

3.88

Input strobe position for bit 3

f = 100 MHz, See Figure 17

4.09

5.00

5.31

ns

Input strobe position for bit 4

6.12

6.43

6.74

Input strobe position for bit 5

7.54

7.85

8.16

Input strobe position for bit 6

8.97

9.28

9.59

f = 85 MHz, See Figure 18

300

RA/RB

ps

f = 100 MHz, See Figure 18

200

CLK OUT Typical period range

10

T

100

ns

CLK OUT Pulse duration, clock high

4.0

5

6.5

CLK OUT Pulse duration, clock low

4.0

5

6.5

f = 85 MHz, See Figure 13

ns

Rax/RBx Setup time to CLK OUT

3.0

Rax/RBx Hold time to CLK OUT

3.5

CLK OUT Pulse duration, clock high

3.0

5.0

CLK OUT Pulse duration, clock low

3.0

5.0

f = 100 MHz, See Figure 13

ns

Rax/RBx Setup time to CLK OUT

2.0

Rax/RBx Hold time to CLK OUT

2.5

RCLK

± to CLK OUT Propagation delay time

6

9

ns

See Figure 15

10

ms

Receiver disable time

See Figure 16

1

µs

(1)

(2)

Receiver skew margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter

pulse positions (min and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows

for LVDS interconnect skew, inter-symbol interference (both dependent on type/length of cable), and clock jitter (less than 150 ps).

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