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ICS91857YLLFT-LF-T Datasheet(PDF) 8 Page - Integrated Circuit Systems |
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ICS91857YLLFT-LF-T Datasheet(HTML) 8 Page - Integrated Circuit Systems |
8 / 14 page 8 ICS91857 0494C—08/15/05 Switching Characteristics for DDRI-400 PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Low-to high level propagation delay time tPLH 1 CLK_IN to any output 3.5 ns High-to low level propagation delay time tPLL 1 CLK_IN to any output 3.5 ns Output enable time tEN PD# to any output 3 ns Output disable time tdis PD# to any output 3 ns Period jitter Tjit (per) 100 - 200 MHz -50 50 ps Half-period jitter t(jit_hper) 100 - 200 MHz -75 75 Input clock slew rate t(sir_I) 14 V/ns Output clock slew rate t(sl_o) 12 V/ns Cycle to Cycle Jitter 1 Tcyc-Tcyc 100 - 200 MHz -75 75 ps Static Phase Offset t(spo) 3 -50 0 50 ps Output to Output Skew Tskew 75 ps Pulse skew Tskewp 100 ps Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. Switching characteristics guaranteed for application frequency range. 3. Static phase offset shifted by design. |
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