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HY62U8200B Datasheet(PDF) 2 Page - Hynix Semiconductor |
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HY62U8200B Datasheet(HTML) 2 Page - Hynix Semiconductor |
2 / 12 page Y62U8200B Series Rev 06 / Apr. 2001 2 DESCRIPTION The HY62U8200B is a high speed, low power and 2M bit CMOS SRAM organized as 262,144 words by 8bit. The HY62U8200B uses high performance CMOS process technology and designed for high speed low power circuit technology. It is particularly well suited for used in high density low power system application. This device has a data retention mode that guarantees data to remain valid at a minimum power supply voltage of 2.0V. FEATURES • Fully static operation and Tri-state output • TTL compatible inputs and outputs • Battery backup( LL-part ) -. 2.0V(min) data retention • Standard pin configuration -. 32-sTSOPI-8X13.4, 32-TSOPI -8X20 (Standard and Reversed) Product No. Voltage (V) Speed (ns) Operation Current/Icc(mA) Standby Current(uA) Temperature ( °C) HY62U8200B 2.7~3.3 70*/85/100 5 25 0~70 HY62U8200B-E 2.7~3.3 70*/85/100 5 25 -25~85(E) HY62U8200B-I 2.7~3.3 70*/85/100 5 25 -40~85(I) Note 1. Blank : Commercial, E : Extended, I : Industrial 2. Current value is max. 3. * measured with 30pF test load PIN CONNECTION TSOP-I sTSOP-I (Standard) (Standard) PIN DESCRIPTION BLOCK DIAGRAM Pin Name Pin Function /CS1 Chip Select 1 CS2 Chip Select 2 /WE Write Enable /OE Output Enable A0 ~ A17 Address Input I/O1 ~ I/O8 Data Input/Output Vcc Power(2.7V~3.3V) Vss Ground MEMORY ARRAY 256K x 8 ROW DECODER I/O1 I/O8 A0 A17 /CS1 CS2 /WE /OE A11 A9 A8 A13 /WE CS2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A11 A9 A8 A13 /WE CS2 A15 Vcc A17 A16 A14 A12 A7 A6 A5 A4 /OE A10 /CS1 DQ8 DQ7 DQ6 DQ5 DQ4 Vss DQ3 DQ2 DQ1 A0 A1 A2 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 |
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