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FMS9875KAC140 Datasheet(PDF) 4 Page - Fairchild Semiconductor |
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FMS9875KAC140 Datasheet(HTML) 4 Page - Fairchild Semiconductor |
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4 / 29 page  PRODUCT SPECIFICATION FMS9875 4 REV. 1.2.15 1/14/02 Pin Descriptions Pin Name Pin No. Type/Value Pin Function Description Converter Channels YGIN, BPIN, RPIN 3, 9, 15 Input Analog Inputs. RGB or YPBPR. YGREF, BPREF, RPREF 4, 10, 16 Input Clamp Reference Inputs. Voltage reference inputs for YG, BP and RP clamps. DYG7-0 76–83 Output Luminance/Green Channel Data Output. DPB7-0 63–70 Output PB/Blue Channel Data Output. DPR7-0 51–58 Output PR/Red Channel Data Output. Timing Generator CLAMP 21 Input External Clamp Input. INVSCK 20 Input Invert Sampling Clock. Inverts SCK, the internal clock sampling the analog inputs. Supports Alternate Pixel Sampling mode for capture pixel rates up to 216Ms/s. XCK 34 Input External Clock input. Enabled if register bit, XCKSEL = H. Replaces PXCK clock generated by PLL. If unused, connect to ground through a 10k Ω resistor. DCK 86 Output Output Data Clock. Clock for strobing output data to external logic. DCK 87 Output Output Data Clock Inverted. Inverted clock for strobing output data to external logic. HSOUT 88 Output Horizontal Sync Output. Reconstructed HSYNC delayed by FMS9875 latency with leading edge synchronized to start of data output. Polarity is always active HIGH. Phase Locked Loop HSIN 30 Schmitt Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source should be clamped at 3.3V or current limited, to prevent overdriving ESD protection diodes. COAST 31 Input PLL COAST. Extraneous or missing horizontal sync pulses can be ignored by asserting the COAST input. With COAST asserted, the HSIN signal is ignored by the PLL without affecting PXCK and the derived clocks: SCK, DCK and DCK. With register bit, COASTPOL = 1: COAST = L: PLL locked to HSIN. COAST = H: PLL VCO input floats with HSIN disregarded COAST polarity may be inverted using the COASTPOL register bit. LPF 35 Passive PLL Low Pass Filter. Connect recommended PLL filter to LPF pin. (see Schematic, PLL Filter) Sync Stripper ACSIN 2 Analog Composite Sync Input. Input to sync stripper with 150mV threshold. DCSOUT 89 Digital Composite Sync Output. Output from sync stripper. Control SDA 22 Bi-directional Serial Port Data. Bi-directional data (I2C/SMBUS). SCL 23 Input Serial Port Clock. Clock input (I2C/SMBUS). A0 24 Input Address bit 0. Lower bit of serial port address. A1 25 Input Address bit 1. Upper bit of serial port address. PWRDN 96 Input Power Down/Output Control. Powers down the FMS9875 with outputs high impedance. |
Similar Part No. - FMS9875KAC140 |
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Similar Description - FMS9875KAC140 |
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