 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MT8979 Datasheet(PDF) 3 Page - Zarlink Semiconductor Inc |
|
||||||||||||||||||||||||||||||
MT8979 Datasheet(HTML) 3 Page - Zarlink Semiconductor Inc |
|
|
3 / 34 page  MT8979 Data Sheet 3 Zarlink Semiconductor Inc. 11 17 ADI Alternate Digit Inversion (Input): If this input is high, the CEPT timeslots which are specified on CSTi0 as voice channels are ADI coded and decoded. When this bit is low it disables ADI coding for all channels. This feature allows either ADI or non-ADI codecs to be used on DSTi and DSTo. 12 19 CSTi0 Control ST-BUS Input #0: A 2048 kbit/s stream that contains 30 per channel control words and two Master Control Words. 13 20 E8Ko Extracted 8 kHz Clock (Output): An 8 kHz output generated by dividing the extracted 2048 kHz clock by 256 and aligning it with the received CEPT frame. The 8 kHz signal can be used for synchronizing the system clock to the extracted 2048 kHz clock. Only valid when device achieves synchronization (goes low during a loss of signal or a loss of basic frame synchronization condition). E8Ko goes high impedance when 8 kHzSEL = 0 in MCW2. 15 23 XCtl External Control (Output): An uncommitted external output pin which is set or reset via bit 1 in Master Control Word 2 on CSTi0. The state of XCtl is updated once per frame. 16 24 XSt External Status: The state of this pin is sampled once per frame and the status is reported in bit 1 of the Master Status Word 1 on CSTo. 17 26 CSTo Control ST-BUS Output: A 2048 kbit/s serial control stream which provides the 16 signalling words, two Master Status Words, Phase Status Word and CRC Error Count. 18 NC No Connection. 19 28 DSTi Data ST-BUS Input: This pin accepts a 2048 kbit/s serial stream which contains the 30 PCM or data channels to be transmitted on the CEPT trunk. 20 NC No Connection. 21 34 C2i 2048 kbit/s System Clock (Input): The master clock for the ST-BUS section of the chip. All data on the ST-BUS is clocked in on the falling edge of the C2i and output on the rising edge. The falling edge of C2i is also used to clock out data on the CEPT transmit link. 22 37 TxMF Transmit Multiframe Boundary (Input): This input can be used to set the channel associated and CRC transmitted multiframe boundary (clear the frame counters). The device will generate its own multiframe if this pin is held high. 23 38 RxMF Received Multiframe Boundary (Output): An output pulse delimiting the received Multiframe boundary. (This multiframe is not related to the received CRC multiframe.) The next frame output on the data stream (DSTo) is received as frame 0 on the CEPT link. 24 NC No Connection. 25 40 E2i Extracted 2048 kHz Clock (Input): The falling edge of this 2048 kHz clock is used to latch the received data (RxD). This clock input must be derived from the CEPT received data and must have its falling edge aligned with the center of the received bit (RxD). Pin Description (continued) Pin # Name Description DIP PLCC |
Similar Part No. - MT8979 |
|
Similar Description - MT8979 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
