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HN58X2464SFPIE Datasheet(PDF) 8 Page - Renesas Technology Corp |
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HN58X2464SFPIE Datasheet(HTML) 8 Page - Renesas Technology Corp |
8 / 22 page HN58X2432SI/HN58X2464SI Rev.2.00, Jan.11.2005, page 8 of 20 Device Address (A0, A1, A2) Eight devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each device and device address pins should be connected to VCC or VSS. When device address code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one device can be activated. These pins are internally pulled-down to VSS. The device read these pins as Low if unconnected. Pin Connections for A0 to A2 Pin connection Memory size Max connect number A2 A1 A0 Notes 32k bit 8 ×* 1 ×* 1 ×* 1 64k bit 8 ×* 1 ×* 1 ×* 1 Notes: 1. × = Don’t care (Open is also approval). Write Protect (WP) When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following table. When the WP is low, write operation for all memory arrays are allowed. WP pin should be fixed high or low status from start condition input to stop condition input. When left unconnected, write operation for all memory arrays are allowed because the WP pin is internally pulled down to VSS. The read operation is always activated irrespective of the WP pin status. Write Protect Area WP pin status Write protect area VIH All memory VIL Normal read/write operation |
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