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UPD30102S1-66-3C Datasheet(PDF) 9 Page - NEC |
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UPD30102S1-66-3C Datasheet(HTML) 9 Page - NEC |
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9 / 701 page  9 CONTENTS CHAPTER 1 INTRODUCTION .............................................................................................................. 29 1.1 FEATURES.............................................................................................................................. 29 1.2 ORDERING INFORMATION .................................................................................................. 30 1.3 64-BIT ARCHITECTURE........................................................................................................ 30 1.4 VR4102 PROCESSOR ............................................................................................................ 30 1.4.1 Internal Block Structure............................................................................................................. 31 1.4.2 I/O Registers ............................................................................................................................... 33 1.5 VR4100 CPU CORE ............................................................................................................... 43 1.5.1 VR4100 CPU Core ....................................................................................................................... 43 1.5.2 CPU Registers ............................................................................................................................ 45 1.5.3 CPU Instruction Set Overview................................................................................................... 46 1.5.4 Data Formats and Addressing .................................................................................................. 47 1.5.5 Coprocessors (CP0-CP3)........................................................................................................... 49 1.5.6 Floating-Point Unit (FPU)........................................................................................................... 51 1.5.7 Cache .......................................................................................................................................... 51 1.6 CPU CORE MEMORY MANAGEMENT SYSTEM (MMU)................................................. 52 1.6.1 Translation Lookaside Buffer (TLB) ......................................................................................... 52 1.6.2 Operating Modes ........................................................................................................................ 52 1.7 INSTRUCTION PIPELINE ...................................................................................................... 53 1.8 CLOCK INTERFACE.............................................................................................................. 53 CHAPTER 2 PIN FUNCTIONS............................................................................................................. 57 2.1 PIN CONFIGURATION...........................................................................................................57 2.2 PIN FUNCTION DESCRIPTION............................................................................................ 62 2.2.1 System Bus Interface Signals ................................................................................................... 63 2.2.2 Clock Interface Signals.............................................................................................................. 65 2.2.3 Battery Monitor Interface Signals ............................................................................................. 65 2.2.4 Initialization Interface Signals................................................................................................... 66 2.2.5 RS-232-C Interface Signals........................................................................................................ 67 2.2.6 IrDA Interface Signals ................................................................................................................ 68 2.2.7 Debug Serial Interface Signals.................................................................................................. 68 2.2.8 Keyboard Interface Signals ....................................................................................................... 69 2.2.9 Audio Interface Signals ............................................................................................................. 69 2.2.10 Touch Panel/General Purpose A/D Interface Signals ........................................................... 69 2.2.11 General-purpose I/O Signals ................................................................................................... 70 2.2.12 HSP MODEM Interface Signals ............................................................................................... 71 2.2.13 LED Interface Signal ................................................................................................................ 71 2.2.14 Dedicated VDD and GND Signals ............................................................................................. 72 2.3 PIN STATUS UPON SPECIFIC STATES ........................................................................... 73 2.3.1 Pin Status upon Reset ............................................................................................................... 73 2.3.2 Connection of Unused Pins and Pin I/O Circuits .................................................................... 76 2.3.3 Pin I/O Circuits ........................................................................................................................... 79 |
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