CY28372
Document #: 38-07533 Rev. *A
Page 2 of 18
Pin Description
Pin #.
Name
Type
Description
6XIN
I
Crystal Connection or External Reference Frequency Input. This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
7XOUT
O
Crystal Connection. Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
4REF2
O
Reference Clock. 14.31818 reference outputs.
2, 3
REF[0:1]/
FS[0:1]
O
Reference Clock. 14.31818 reference outputs.
I
Frequency Select. Sampled upon power-on to determine device operating frequency.
14, 15
PCIF[0:1]/
FS[2:3]
O
Free-running PCI. Independent of PCI_STP#.
I
Frequency Select. Sampled upon power-on to determine device operating frequency.
16, 17, 20,
21, 22, 23
PCI [0:5]
O
PCI Clock.
12
PCI_STP#
I
PCI Stop. Stops all PCI clocks
40
39
CPUT0
CPUC0
O
Differential CPU Outputs.
43
CPUT1
O
“True” Clock of Differential CPU Outputs. For chipset host bus
44
CPU_STP#
I
CPU Stop. Stops all CPU clocks
9, 10
ZCLK[0:1]
O
MuTIOL Clock Outputs.
46, 47
IOAPIC[0:1]
O
IOAPIC. 2.5 V clock outputs
27
48MHz
O
48-MHz Clock. USB clock outputs
26
24_48MHz
O
24-MHz or 48-MHz Clock. Selectable SIO clock outputs. Default output frequency is
24 MHz, but can be configured for 48 MHz through I2C.
31, 30
AGP[0:1]
O
AGP Clock.
34
SDATA
I/O
I2C Data. 5v tolerant
35
SCLK
I
I2C Clock.5v tolerant
33
PD#
I
Power-down Control. Turns off all clock outputs and shuts down device
36
VDDA
PWR
3.3V Analog Power/Ground. Power supply for core logic, PLL circuitry
37
GNDA
PWR
1, 5, 8, 11,
13, 18, 19,
24, 25, 28,
29, 32
VDD_REF,
GND_REF,
GND_Z,
VDD_Z,
VDD_PCI,
GND_PCI,
GND_48,
VDD_48,
VDD_AGP,
GND_AGP
PWR
3.3V Power and Ground. Power supply for respective output buffers.
38, 41, 42
48, 45
VDD_CPU,
GND_CPU,
VDD_APIC,
GND_APIC
PWR
2.5V Power and Ground. Power supply for respective output buffers.
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