AnyClock™

SY87729L

6

Micrel

123412312341

12

3

1

Figure 2. 11/3 Example

Figure 2 shows an example generating an output

frequency is between 3 and 4 times the input, P is set to 4.

We need to select the P divider twice, and select the P-1

divider once. Multiplying by 4 two times out of three, and

multiplying by 3 one time out of three, averages to a

The top waveform is the reference input. The bottom

waveform is the multiplied output. The waveform in the

middle shows those edges from the output that most closely

matches a corresponding reference waveform edge.

The control circuit must generate a repeating pattern to

the mux of something like “101,” so that the P divider is

selected twice, and the P-1 divider is selected once, every

three reference edges.

Fractional-N Phase-Frequency Detector

This circuit, besides generating “pump up” and “pump

down” signals, also generates delta phase signals for use

by the lock detect circuit.

This detector circuit also accepts a gating signal from the

Fractional-N control block. When gated, the phase detector

generates neither pump up nor pump down pulses.

Fractional-N Charge Pump

This circuit converts the “pump up” and “pump down”

signals from the phase-frequency detector into current

pulses. An external loop filter integrates these current pulses

into a control voltage.

Charge pump current is selectable. This modifies loop

gain as follows:

During acquisition of the reference, the charge pump

current is fixed at 20

µA. Once the acquisition sequencer

has completed center frequency trimming, then it changes

the current of this charge pump to 50

µA.

Fractional-N VCO

This circuit converts the voltage integrated by the external

loop filter into a digital clock stream. The frequency of this

clock varies based on this control voltage. This VCO has a

coarse and a fine input, with a combined range of 540MHz

to 729MHz. The coarse input trims the VCO, as described

below, so that its center frequency rests near the target

frequency to generate. The fine adjustment forms part of

the closed loop. VCO gain is nominally 200MHz per Volt.

Fractional-N P/P-1 Divider

This is the main divider for the fractional-N loop. The

logical value of the output of the control block (Figure 1)

defines whether the divider divides by P (values shown in

Table 1) or by P-1. The expression for the fractional division

becomes:

Fractional division

P –

Q

QQ

P–1

P–1P

=

+

()

















of reference clock periods during which the divider must

divide by P-1.

Care should be exercised when selecting the value of P

(Table 1) so that the voltage-controlled oscillator (VCO) of

the fractional-N PLL is not driven out of range. The following

conditions must be met:

f

(min)

f

Fractional division

f

(max)

VCO

REF

VCO

<<

×

or

f

(min)

f

P –

Q

QQ

f

(max)

VCO

REF

P–1

P–1P

VCO

<<

×

+

()

































Where,

DivSel3

DivSel2

DivSel1

DivSel0

P

00

0

0

17

00

0

1

18

00

1

0

19

00

1

1

20

01

0

0

21

01

0

1

22

01

1

0

23

01

1

1

24

10

0

0

25

10

0

1

26

10

1

0

27

10

1

1

28

11

0

0

29

11

0

1

30

11

1

0

31

11

1

1

32

Table 1. DivSel Divider Setting

Fractional-N Control

This circuit controls the P/P-1 divider, selecting the

appropriate divide ratio, either P or P-1, in the correct pattern.

As explained in the example of Figure 2 above, controlling

the P/P-1 divider amounts to generating a repeating binary

bit stream. In that example, a “1” represents dividing by 4,

and a “0” represents dividing by 3. The full cycle, “101,”

says to divide by 4 twice, and to divide by 3 once.