SN65LVDS388, SN65LVDT388, SN75LVDS388, SN75LVDT388

HIGH-SPEED DIFFERENTIAL LINE RECEIVERS

SLLS448A – SEPTEMBER 2000 – REVISED MAY 2001

1

POST OFFICE BOX 655303

Requirements of ANSI TIA/EIA-644

Standard

Resistors on LVDT Products

630 Mbps

15 kV

Part-To-Part Skew Is Less Than 1 ns

Package With 20-mil Terminal Pitch

description

The ‘LVDS388 and ‘LVDT388 (T designates

integrated termination) are eight differential line

receivers that implement the electrical character-

istics of low-voltage differential signaling (LVDS).

This signaling technique lowers the output voltage

levels of 5-V differential standard levels (such as

EIA/TIA-422B) to reduce the power, increase the

switching speeds, and allow operation with a 3-V

supply rail. Any of the eight differential receivers

will provide a valid logical output state with a

+100-mV differential input voltage within the input

common-mode

voltage

range.

The

input

common-mode voltage range allows 1 V of

ground potential difference between two LVDS

nodes. Additionally, the high-speed switching of

LVDS signals always require the use of a line

impedance matching resistor at the receiving end

of the cable or transmission media. The LVDT

product eliminates this external resistor by

integrating it with the receiver.

Copyright

 2001, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

’LVDx388

1A

1B

2A

2B

1Y

2Y

’LVDT388 ONLY

EN

(1/4 of ’LVDx388 shown)

logic diagram (positive logic)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

GND

ENA

A1Y

A2Y

ENB

B1Y

B2Y

GND

GND

C1Y

C2Y

ENC

D1Y

D2Y

END

GND

A1A

A1B

A2A

A2B

NC

B1A

B1B

B2A

B2B

NC

C1A

C1B

C2A

C2B

NC

D1A

D1B

D2A

D2B

’LVDS388, ’LVDT388

DBT PACKAGE

(TOP VIEW)

NOT RECOMMENDED FOR NEW DESIGNS

For Replacement Use ’LVDx388A

† Signaling rate, 1/t, where t is the minimum unit interval and is expressed in the units bits/s (bits per second)