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IR3094PBF Datasheet(PDF) 11 Page - International Rectifier

Part # IR3094PBF
Description  3 PHASE PWM CONTROLLER FOR POINT OF LOAD
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

IR3094PBF Datasheet(HTML) 11 Page - International Rectifier

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IR3094PBF
Page 11 of 29
09/26/05
PWM Operation
The IR3094 is a fully integrated 3 phase interleaved PWM control IC which uses voltage mode control with trailing
edge modulation. A high-gain wide-bandwidth voltage type Error Amplifier in the Control IC is used for the voltage
control loop. The PWM block diagram of the IR3094 is shown in Figure 2.
S
Q
QB
R
OVP LATCH
CSINM2
CSINM1
9p
9p
VDRP BUFFER
RESET DOMINANT
RESET DOMINANT
0.575V
IROSC
-
+
PWM COMPARATOR
0 TO IROSC*3/4
+
-
Share Adjust Error Amp
IROSC
ERROR AMPLIFIER
0.6V
RCS2
S
Q
QB
R
RSFF
CSC2
IROSC/2
CCS1
1
2
-
+
PWM COMPARATOR
CCS2
RSC2
RCS1
CCOMP
CDAC
VDAC
0% DUTY CYCLE
RFB
CLK2
S
Q
QB
R
RSFF
RDRP
RCOMP
RDAC
0.6V
COUT
1
2
VREF
VDRP
EAOUT
SCOMP2
GATEL1
GATEH1
GATEH2
CSINP1
GATEL2
CSINP2
CSINM3
FB
VOSNS-
VOUT SENSE+
VOUT SENSE-
VOUT-
VOUT+
VDAC
-
+
X23.5
CSINP3
RESET DOMINANT
9p
IROSC
-
+
PWM COMPARATOR
0 TO IROSC*3/4
+
-
Share Adjust Error Amp
S
Q
QB
R
RSFF
0.6V
RCS3 CCS3
1
2
GATEH3
GATEL3
VIN
CSC3
SCOMP3
RSC3
VIN
VIN
VDAC
-
+
X23.5
VDAC
-
+
X23.5
CLK3
CLK2
EAOUT
CLK1
CLK2
IROSC
CLK3
U30
OSCBLOCK
CLK3
OVP SET
OVP RESET
Figure 2 – PWM Block Diagram
Refer to Figure 3. Upon receiving a clock pulse, the RSFF is set, the internal PWM ramp voltage begins to
increase, the low side driver is turned off, and the high side driver is then turned on. For phase 1, an internal 9pf
capacitor is charged by a current source that proportional to the switching frequency resulting in a ramp rate of
50mV per percent duty cycle. For example, if the steady-state operating switch node duty cycle is 10%, then the
internal ramp amplitude is typically 500mV from the starting point (or floor) to the crossing of the EAOUT control
voltage. When the PWM ramp voltage exceeds the Error Amplifier’s output voltage, the RSFF is reset. This turns
off the high side driver, turns on the low side driver, and discharges the PWM ramp to 0.6V until the next clock
pulse.


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