7

IDTCSPT857D

2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER

COMMERCIALANDINDUSTRIALTEMPERATURERANGES

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200

FollowingConditionsApplyUnlessOtherwiseSpecified:

Symbol

Parameter

Conditions

Min.

Typ.

Max.

Unit

InputClampVoltage(AllInputs)



– 1.2

V

StaticInputLOWVoltage

PWRDWN

– 0.3



0.7

V

Static Input HIGH Voltage

PWRDWN

1.7



DynamicInputLOWVoltage

CLK, CLK, FBIN, FBIN



0.7

V

Dynamic Input HIGH Voltage

CLK, CLK, FBIN, FBIN

1.7

OutputLOWVoltage

µA



0.1

V



0.6

Output HIGH Voltage

V

1.7

InputDifferentialCrossVoltage

V

DCInputDifferentialVoltage

0.36

V

ACInputDifferentialVoltage

0.7

V

InputCurrent

±10

µA



100

200

µA

Ω/14pF



320

360

mA

Ω/14pF



250

300



12

mA

NOTE:

TIMING REQUIREMENTS FOR PC3200

Symbol

Parameter

Min.

Max.

Unit

60

220

MHz

60

220

MHz

Input Clock Duty Cycle

40

60

%



100

µs

NOTES:

1. The PLL will track a spread spectrum clock input.

2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.

3. Application clock frequency is the range over which timing specifications apply.

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.

TIMING REQUIREMENTS FOR PC1600 - PC2700

Symbol

Parameter

Min.

Max.

Unit

60

200

MHz

60

200

MHz

Input Clock Duty Cycle

40

60

%



100

µs

NOTES:

1. The PLL will track a spread spectrum clock input.

2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications.

3. Application clock frequency is the range over which timing specifications apply.

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.