M34E02-FMB1TP datasheet(7/23 Pages) STMICROELECTRONICS

Part #	M34E02-FMB1TP

Description	2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs

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M34E02

DEVICE OPERATION

The device supports the I2C protocol. This is sum-

marized in Figure 5. Any device that sends data on

to the bus is defined to be a transmitter, and any

device that reads the data to be a receiver. The

device that controls the data transfer is known as

the bus master, and the other as the slave device.

A data transfer can only be initiated by the bus

master, which will also provide the serial clock for

synchronization. The memory device is always a

slave in all communication.

Start Condition

Start is identified by a falling edge of Serial Data

(SDA) while Serial Clock (SCL) is stable in the

High state. A Start condition must precede any

data transfer command. The device continuously

monitors (except during a Write cycle) Serial Data

(SDA) and Serial Clock (SCL) for a Start condition,

and will not respond unless one is given.

Stop Condition

Stop is identified by a rising edge of Serial Data

(SDA) while Serial Clock (SCL) is stable and driv-

en High. A Stop condition terminates communica-

tion between the device and the bus master. A

Read command that is followed by NoAck can be

followed by a Stop condition to force the device

into the Stand-by mode. A Stop condition at the

end of a Write command triggers the internal EE-

PROM Write cycle.

Acknowledge Bit (ACK)

The acknowledge bit is used to indicate a success-

ful byte transfer. The bus transmitter, whether it be

bus master or slave device, releases Serial Data

(SDA) after sending eight bits of data. During the

9th clock pulse period, the receiver pulls Serial

Data (SDA) Low to acknowledge the receipt of the

eight data bits.

Data Input

During data input, the device samples Serial Data

(SDA) on the rising edge of Serial Clock (SCL).

For correct device operation, Serial Data (SDA)

must be stable during the rising edge of Serial

Clock (SCL), and the Serial Data (SDA) signal

must change

only when Serial Clock (SCL) is driv-

en Low.

Memory Addressing

To start communication between the bus master

and the slave device, the bus master must initiate

a Start condition. Following this, the bus master

sends the Device Select Code, shown in Table 2

(on Serial Data (SDA), most significant bit first).

The Device Select Code consists of a 4-bit Device

Type Identifier, and a 3-bit Chip Enable “Address”

(E2, E1, E0). To address the memory array, the 4-

bit Device Type Identifier is 1010b; to access the

write-protection settings, it is 0110b.

Up to eight memory devices can be connected on

a single I2C bus. Each one is given a unique 3-bit

code on the Chip Enable (E0, E1, E2) inputs.

When the Device Select Code is received, the

device only responds if the Chip Enable Address

is the same as the value on the Chip Enable (E0,

E1, E2) inputs.

The 8th bit is the Read/Write bit (RW). This bit is

set to 1 for Read and 0 for Write operations.

If a match occurs on the Device Select code, the

corresponding device gives an acknowledgment

on Serial Data (SDA) during the 9th bit time. If the

device does not match the Device Select code, it

deselects itself from the bus, and goes into Stand-

by mode.

Table 3. Operating Modes

Note: 1. X =

VIH or VIL.

Mode

RW bit

WC 1

Bytes

Initial Sequence

Current Address Read

1

X

1

START, Device Select, RW = 1

Random Address Read

0X

1

START, Device Select, RW = 0, Address

1

X

reSTART, Device Select, RW = 1

Sequential Read

1

X

≥ 1

Similar to Current or Random Address Read

Byte Write

0

VIL

1

START, Device Select, RW = 0

Page Write

0

VIL

≤ 16

START, Device Select, RW = 0

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