11

8Mb: 512K x 18, 256K x 32/36 Flow-Through SyncBurst SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT58L512L18F_2.p65 – Rev. 7/00

©2000, Micron Technology, Inc.

8Mb: 512K x 18, 256K x 32/36

FLOW-THROUGH SYNCBURST SRAM

FBGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL

TYPE

DESCRIPTION

9A

9A

ADV#

Input

Synchronous Address Advance: This active LOW input is used to

advance the internal burst counter, controlling burst access after

the external address is loaded. A HIGH on ADV# effectively causes

wait states to be generated (no address advance). To ensure use of

correct address during a WRITE cycle, ADV# must be HIGH at the

rising edge of the first clock after an ADSP# cycle is initiated.

9B

9B

ADSP#

Input

Synchronous Address Status Processor: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ is performed using the new address,

independent of the byte write enables and ADSC#, but dependent

upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-

down state is entered if CE2 is LOW or CE2# is HIGH.

8A

8A

ADSC#

Input

Synchronous Address Status Controller: This active LOW input

interrupts any ongoing burst, causing a new external address to be

registered. A READ or WRITE is performed using the new address if

CE# is LOW. ADSC# is also used to place the chip into power-down

state when CE# is HIGH.

1R

1R

MODE

Input

Mode: This input selects the burst sequence. A LOW on this

(LB0#)

input selects “linear burst.” NC or HIGH on this input selects

“interleaved burst.” Do not alter input state while device is

operating.

DQa

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated DQas;

10L, 10M, 11D, 10L, 10M, 11J,

Output Byte “b” is associated with DQbs. For the x32 and x36 versions,

11E, 11F, 11G 11K, 11L, 11M

Byte “a” is associated with DQas; Byte “b” is associated with DQbs;

DQb

Byte “c” is associated with DQcs; Byte “d” is associated with DQds.

1L, 1M, 2D,

10F, 10G, 11D,

Input data must meet setup and hold times around the rising edge

2E, 2F, 2G

11E, 11F, 11G

of CLK.

DQc

1F, 1G, 2D,

2E, 2F, 2G

DQd

1M, 2J, 2K,

2L, 2M

11C

11N

NC/

No Connect/Parity Data I/Os: On the x32 version, these are No

1N

11C

I/O

Connect (NC). On the x18 version, Byte “a” parity is DQPa; Byte “b”

–

1C

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

–

1N

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

4D, 4E, 4F,

4D, 4E, 4F,

Supply Power Supply: See DC Electrical Characteristics and Operating

4G, 4H, 4J,

4G, 4H, 4J,

Conditions for range.

4K, 4L, 4M,

4K, 4L, 4M,

8D, 8E, 8F,

8D, 8E, 8F,

8G, 8H, 8J,

8G, 8H, 8J,

8K, 8L, 8M

8K, 8L, 8M

(continued on next page)