128K x 24 Static RAM
CY7C1024AV33
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-05149 Rev. *B
Revised November 13, 2002
024AV33
Features
• High speed
—tAA = 10 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Automatic power-down when deselected
• Easy memory expansion with CE1, CE2, CE3 and OE
options
Functional Description[1]
The CY7C1024AV33 is a high-performance CMOS static RAM
organized as 131,072 words by 24 bits. Easy memory expan-
sion is provided by an active LOW CE1, CE3, active HIGH
CE2, an active LOW Output Enable (OE), and three-state driv-
ers. This device has an automatic power-down feature that
significantly reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE1, CE2, CE3) active and Write Enable (WE) inputs LOW.
Data on the 24 I/O pins (I/O0 through I/O23) is then written into
the location specified on the address pins (A0 through A16).
Reading from the device is accomplished by taking Chip
Enable (CE1, CE2, CE3) active and Output Enable (OE) LOW
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The 24 input/output pins (I/O0 through I/O23) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE1, CE3 LOW, CE2 HIGH, and WE LOW).
The CY7C1024AV33 is available in a standard 119-ball BGA
package and a 100-pin TQFP package.
Functional Block Diagram
MEMORY ARRAY
COLUMN
DECODER
128K X 24
A16
A0
CONTROL
CE#
CE1#
CE2
WE#
OE#
DQ0
DQ23
VCC
VSS
Selection Guide
7C1024AV33-10
7C1024AV33-12
7C1024AV33-15
Maximum Access Time (ns)
10
12
15
Maximum Operating Current (mA)
275
250
225
Maximum Standby Current (mA)
15
15
15
Note:
1.
For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
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