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HT83036 Datasheet(PDF) 11 Page - Holtek Semiconductor Inc |
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HT83036 Datasheet(HTML) 11 Page - Holtek Semiconductor Inc |
11 / 21 page HT83XXX Rev. 0.10 11 August 25, 2003 Preliminary Address RAM Mapping Read/Write Description 0AH STATUS R/W Status register 0BH INTC R/W Interrupt control register 0 0DH TMR0 R/W Timer counter 0 register 0EH TMR0C R/W Timer counter 0 control register 10H TMR1 R/W Timer counter 1 register 11H TMR1C R/W Timer counter 1 control register 12H PA R/W Port A I/O data register 13H PAC R/W Port A I/O control register 18H LATCH0H R/W Voice ROM address latch 0 [A17, A16] 19H LATCH0M R/W Voice ROM address latch 0 [A15~A8] 1AH LATCH0L R/W Voice ROM address latch 0 [A7~A0] 26H PWMCR R/W PWM control register 28H PWMD R/W PWM output data D7~D0 2AH LATCHD R Voice ROM data register 2BH~2FH Unused 30H~7FH User data RAM R/W User data RAM Note: R: Read only W: Write only R/W: Read/Write Indirect Addressing Register Location 00H is indirect addressing registers that are not physically implemented. Any read/write operation of [00H] accesses the RAM pointed to by MP0 (01H) re- spectively. Reading location 00H indirectly returns the result 00H. While, writing it indirectly leads to no opera- tion. Accumulator - ACC (05H) The accumulator (ACC) is related to the ALU opera- tions. It is also mapped to location 05H of the RAM and is capable of operating with immediate data. The data movement between two data memory locations must pass through the ACC. Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions and provides the following functions: · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ etc) Status Register - STATUS (0AH) This 8-bit STATUS register (0AH) consists of a zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), watchdog time-out flag (TO). It also records the status information and controls the operation sequence. Except the TO and PDF flags, bits in the status register can be altered by instructions similar to other registers. Data written into the status register does not alter the TO or PDF flags. Operations related to the status register, however, may yield different results from those in- tended. The TO and PDF flags can only be changed by a Watchdog Timer overflow, chip power-up, or clearing the Watchdog Timer and executing the ²HALT² instruc- tion. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automati- cally pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. |
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