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S87L51FB-4A44 Datasheet(PDF) 9 Page - NXP Semiconductors

Part # S87L51FB-4A44
Description  CMOS single-chip 3.0V 8-bit microcontrollers
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

S87L51FB-4A44 Datasheet(HTML) 9 Page - NXP Semiconductors

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Philips Semiconductors
Product specification
87L51FA/87L51FB
CMOS single-chip 3.0V 8-bit microcontrollers
1996 Aug 16
3-158
AC ELECTRICAL CHARACTERISTICS
Tamb = 0°C to +70°C, –40 to +85°C, VCC = 3.0V to 4.5V, VSS = 0V1, 2, 3
16MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/tCLCL
1
Oscillator frequency
–4, –5
3.5
16
MHz
–7, –8
3.5
20
MHz
tLHLL
1
ALE pulse width
85
2tCLCL–40
ns
tAVLL
1
Address valid to ALE low
22
tCLCL–40
ns
tLLAX
1
Address hold after ALE low
32
tCLCL–30
ns
tLLIV
1
ALE low to valid instruction in
150
4tCLCL–100
ns
tLLPL
1
ALE low to PSEN low
32
tCLCL–30
ns
tPLPH
1
PSEN pulse width
142
3tCLCL–45
ns
tPLIV
1
PSEN low to valid instruction in
82
3tCLCL–105
ns
tPXIX
1
Input instruction hold after PSEN
0
0
ns
tPXIZ
1
Input instruction float after PSEN
37
tCLCL–25
ns
tAVIV
1
Address to valid instruction in
207
5tCLCL–105
ns
tPLAZ
1
PSEN low to address float
10
10
ns
Data Memory
tRLRH
2, 3
RD pulse width
275
6tCLCL–100
ns
tWLWH
2, 3
WR pulse width
275
6tCLCL–100
ns
tRLDV
2, 3
RD low to valid data in
147
5tCLCL–165
ns
tRHDX
2, 3
Data hold after RD
0
0
ns
tRHDZ
2, 3
Data float after RD
65
2tCLCL–60
ns
tLLDV
2, 3
ALE low to valid data in
350
8tCLCL–150
ns
tAVDV
2, 3
Address to valid data in
397
9tCLCL–165
ns
tLLWL
2, 3
ALE low to RD or WR low
137
237
3tCLCL–50
3tCLCL+50
ns
tAVWL
2, 3
Address valid to WR low or RD low
122
4tCLCL–130
ns
tQVWX
2, 3
Data valid to WR transition
13
tCLCL–50
ns
tWHQX
2, 3
Data hold after WR
13
tCLCL–50
ns
tQVWH
3
Data valid to WR high
287
7tCLCL–150
ns
tRLAZ
2, 3
RD low to address float
0
0
ns
tWHLH
2, 3
RD or WR high to ALE high
23
103
tCLCL–40
tCLCL+40
ns
External Clock
tCHCX
5
High time
12
20
ns
tCLCX
5
Low time
12
20
ns
tCLCH
5
Rise time
20
20
ns
tCHCL
5
Fall time
20
20
ns
Shift Register
tXLXL
4
Serial port clock cycle time
1
12tCLCL
µs
tQVXH
4
Output data setup to clock rising edge
492
10tCLCL–133
ns
tXHQX
4
Output data hold after clock rising edge
8
2tCLCL–117
ns
tXHDX
4
Input data hold after clock rising edge
0
0
ns
tXHDV
4
Clock rising edge to input data valid
492
10tCLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 87L51FA/FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.


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