Pin Capacitance

(f = 1 MHz, T = 25°C)

(1)

Typ

Max

Units

Conditions

58

pF

68

pF

Note:

1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.

Power Up Reset

The registers in the AT22V10 and AT22V10L are designed to

crossing 3.8 V, all registers will be reset to the low state. The

output state will depend on the polarity of the output buffer.

This feature is critical for state machine initialization. However,

due to the asynchronous nature of reset and the uncertainty of

are required:

2) After reset occurs, all input and feedback setup times must be

met before driving the clock pin high, and

Parameter

Description

Min

Typ

Max

Units

Power-Up

Reset Time

600

1000

ns

CLOCK

3.8 V

POWER

REGISTERED

OUTPUTS

tS

tPR

tW

Erasure Characteristics

The entire fuse array of an AT22V10 or AT22V10L is erased

after exposure to ultraviolet light at a wavelength of 2537 Å.

Complete erasure is assured after a minimum of 20 minutes ex-

posure using 12,000

away from the chip. Minimum erase time for lamps at other in-

tensity ratings can be calculated from the minimum integrated

sure, an opaque label is recommended to cover the clear window

on any UV erasable PLD which will be subjected to continuous

fluorescent indoor lighting or sunlight.

Preload of Registered Outputs

The registers in the AT22V10 and AT22V10L are provided

with circuitry to allow loading of each register asynchronously

with either a high or a low. This feature will simplify testing

since any state can be forced into the registers to control test

setting. The preload state is entered by placing an 11.5-V to

13-V signal on pin 8 on DIPs, and pin 10 on SMPs. When the

clock pin is pulsed high, the data on the I/O pins is placed into

the ten registers.

CLOCK

VH

OUTPUTS

DISABLED

PRELOAD

CLOCKED IN

PRELOAD DATA

PRELOAD

REGISTERED

VOLTAGE

REMOVED

tD

tD

tD

tD

tD

OUTPUT

FORCE I/O’S

TO VIH ORVIL

PRELOAD ENA.

OUTPUTS DIS.

Level forced on

registered output pin

during preload cycle

Register state

after cycle

High

Low

1-102

AT22V10/L