The reduction in characteristic impedance is approxi-

mated by the following formula:

where:

pedance

N = number of capacitive loads

L = trace length

Ω, the loaded differential

impedance is:

Ω

In this example, capacitive loading reduces the charac-

teristic impedance from 120

Ω to 54Ω. The load seen by

a driver located on a card in the middle of the bus is

27

Ω because the driver sees two 54Ω loads in parallel.

A typical LVDS driver (rated for a 100

Ω load) would not

develop a large enough differential signal to be reliably

detected by an LVDS receiver. Maxim’s BLVDS driver is

designed and specified to drive a 27

Ω load to differen-

tial voltage levels of 250mV to 450mV (which are stan-

dard LVDS driver levels). A standard LVDS receiver is

able to detect this level of differential signal.

Short extensions off the bus, called stubs, contribute to

capacitive loading. Keep stubs less than 1in for a good

balance between ease of component placement and

good signal integrity.

The MAX9129 is a current source driver and drives

larger differential signal levels into loads higher than

27

Ω and smaller levels into loads less than 27Ω (see

typical operating curves). To keep loading from reduc-

ing bus impedance below the rated 27

Ω load, PC

board traces can be designed for higher unloaded

characteristic impedance.

Effect of Transition Time

For transition times (measured from 0% to 100%) short-

er than the delay between capacitive loads, the loads

are seen as low-impedance discontinuities from which

the driven signal is reflected. Reflections add and sub-

tract from the signal being driven and cause decreased

noise margin and jitter. The MAX9129 is designed for a

minimum transition time of 1ns (rated 0.6ns from 20% to

80%, or about 1ns 0% to 100%) to reduce reflections

while being fast enough for high-speed backplane data

transmission.

Power-On Reset

The power-on reset voltage of the MAX9129 is typically

2.25V. When the supply falls below this voltage, the

device is disabled and the outputs are in high imped-

ance.

Applications Information

Power-Supply Bypassing

ceramic 0.1µF and 0.001µF capacitors in parallel as

close to the device as possible, with the smaller valued

Termination

In the example above, the loaded differential imped-

ance of the bus is reduced to 54

Ω. Since it can be dri-

ven from any card position, the bus must be terminated

at each end. A parallel termination of 54

Ω at each end

of the bus placed across the traces that make up the

differential pair provides a proper termination. The total

load seen by the driver is 27

Ω.

The MAX9129 drives higher differential signal levels

into lighter loads. A multidrop bus with the driver at one

end and receivers connected at regular intervals along

the bus has a lowered impedance due to capacitive

loading. Assuming the same impedance calculated in

the multidrop example above (54

Ω), the multidrop bus

can be terminated with a single, parallel-connected

54

Ω resistor at the far end from the driver. Only a single

resistor is required because the driver sees one 54

Ω

differential trace. The signal swing is larger with a 54

Ω

load.

In general, parallel terminate each end of the bus with a

resistor matching the differential impedance of the bus

(taking into account any reduced impedance due to

loading).

Board Layout

A four-layer PC board that provides separate power,

ground, input, and output signals is recommended.

Keep the LVTTL/LVCMOS and BLVDS signals separat-

ed to prevent coupling as shown in the suggested lay-

out for the QFN package (not drawn to scale) (Figure 6).

Quad Bus LVDS Driver with

Flow-Through Pinout

8

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