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CY7C1367C-200AXC Datasheet(PDF) 8 Page - Cypress Semiconductor

Part # CY7C1367C-200AXC
Description  9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM
Download  27 Pages
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Manufacturer  CYPRESS [Cypress Semiconductor]
Direct Link  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1367C-200AXC Datasheet(HTML) 8 Page - Cypress Semiconductor

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PRELIMINARY
CY7C1366C
CY7C1367C
Document #: 38-05542 Rev. *A
Page 8 of 27
automatically three-stated whenever a write cycle is detected,
regardless of the state of OE.
Burst Sequences
The CY7C1366C/CY7C1367C provides a two-bit wraparound
counter, fed by A[1:0], that implements either an interleaved or
linear burst sequence. The interleaved burst sequence is
designed specifically to support Intel® Pentium applications.
The linear burst sequence is designed to support processors
that follow a linear burst sequence. The burst sequence is user
selectable through the MODE input. Both read and write burst
operations are supported.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both read and write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CEs, ADSP, and ADSC must remain
inactive for the duration of tZZREC after the ZZ input returns
LOW.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
Partial Truth Table for Read/Write[5, 10]
Function (CY7C1366C)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
XXXX
Read
H
L
HHHH
Write Byte A – (DQA and DQPA)
H
L
HHH
L
Write Byte B – (DQB and DQPB)H
L
H
H
L
H
Write Bytes B, A
H
L
H
H
L
L
Write Byte C – (DQC and DQPC)
H
LH
LH
H
Write Bytes C, A
H
L
H
L
H
L
Write Bytes C, B
H
L
H
L
L
H
Write Bytes C, B, A
H
L
H
L
L
L
Write Byte D – (DQD and DQPD)
H
L
L
HHH
Write Bytes D, A
H
L
L
H
H
L
Write Bytes D, B
H
L
L
H
L
H
Write Bytes D, B, A
H
L
L
H
L
L
Write Bytes D, C
H
L
L
L
H
H
Write Bytes D, C, A
H
L
L
L
H
L
Write Bytes D, C, B
H
LLLL
H
Write All Bytes
H
LLLLL
Write All Bytes
L
XXXXX
Truth Table for Read/Write[5, 10]
Function (CY7C1367C)
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write Byte A – (DQA and DQPA)H
L
H
L
Write Byte B – (DQB and DQPB)H
L
L
H
Write All Bytes
H
L
L
L
Write All Bytes
L
X
X
X


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