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AT24C256SC-09AT Datasheet(PDF) 6 Page - ATMEL Corporation |
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AT24C256SC-09AT Datasheet(HTML) 6 Page - ATMEL Corporation |
6 / 13 page 6 AT24C128SC/AT24C256SC 1661B–SEEPR–04/04 Timing Diagrams Bus Timing Figure 3. Bus Timing Note: SCL: Serial Clock; SDA: Serial Data I/O Write Cycle Timing Figure 4. Write Cycle Timing Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. SCL: Serial Clock; SDA: Serial Data I/O Data Validity Figure 5. Data Validity tWR(1) SDA SCL DATA STABLE DATA CHANGE DATA STABLE |
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