(5/10)

2000-02-18 (Ver.2.4)

LTM10C348S

TIMING SPECIFICATION

1)2) 3) 4)5)

Item

Symbol

Min.

Typ.

Max.

Unit

Remarks

Frame Period

t1

604

× t3

-

628

× t3

16.58

677

× t3

17.86

-

ms

Vertical

Display Term

t2

600

× t3

600

× t3

600

× t3

-

One Line Scanning

Time

t3

958

× t5

26.3

1056

× t5

26.4

1064

× t5

-

µs

Horizontal

Display Term

t4

800

× t5

800

× t5

800

× t5

-

Clock Period

t5

24.7

25.0

27.8

ns

Note 1) Refer to TIMING CHART and LVDS (DF90CF364MTD) specifications by National Semiconductor.

Note 2) If ENAB is fixed to "H" or "L" level for certain period while NCLK is supplied, the panel displays black with some

flicker.

Note 3) If NCLK is fixed to "H" or "L" level for certain period while ENAB is supplied, the panel may be damaged.

Note 4) Please adjust LCD operating signal timing and FL driving frequency, to optimize the display quality.

There is a possibility that flicker is observed by the interference of LCD operating signal timing and FL driving

Condition (especially driving frequency ), even if the condition satisfies above timing specifications and

recommended operating conditions shown in 3.

Note 5) Do not make t1,t2 and t3 fluctuate.

If t1,t2 and t3 are fluctuate, the panel displays black.

Notes 6)

Do not hold NCLK on “H” level nor

“L” level during VDD(+3.3V) Is supplied.

When it holds on, DC voltage

supplies to liquid crystal materials and it may cause damage to liquid crystal materials.

SEQUENCE OF POWER SUPPLIES AND SIGNALS

NCLK

DATA

ENAB

3.0V

3.0V

0.2V

0.2V

0.2V

0.2

0.2

0ms(Min.)

40ms(Max.)

10ms(Max.)

10ms(Max.)

500ms(Min.)

0ms(Min.)

40ms(Max.)