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CHRONTEL
CH7013B
10
201-0000-069
Rev. 1.2, 9/1/2004
In this mode the S[7:0] contains the following data:
S[6]
=
F
=
1 during field 2, 0 during field 1
S[5]
=
V
=
1 during field blanking, 0 elsewhere
S[4]
=
H
=
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3:0] are ignored.
Figure 5: Multiplexed Pixel Data Transfer Mode (IDF = 6)
Table 9. YCrCb Multiplexed Mode with Embedded Syncs
IDF#
Format
9
YCrCb 8-bit
Pixel#
P0a
P0b
P1a
P1b
P2a
P2b
P3a
P3b
Bus Data
D[7]
1
0
0
S[7]
Cb2[7]
Y2[7]
Cr2[7]
Y3[7]
D[6]
1
0
0
S[6]
Cb2[6]
Y2[6]
Cr2[6]
Y3[6]
D[5]
1
0
0
S[5]
Cb2[5]
Y2[5]
Cr2[5]
Y3[5]
D[4]
1
0
0
S[4]
Cb2[4]
Y2[4]
Cr2[4]
Y3[4]
D[3]
1
0
0
S[3]
Cb2[3]
Y2[3]
Cr2[3]
Y3[3]
D[2]
1
0
0
S[2]
Cb2[2]
Y2[2]
Cr2[2]
Y3[2]
D[1]
1
0
0
S[1]
Cb2[1]
Y2[1]
Cr2[1]
Y3[1]
D[0]
1
0
0
S[0]
Cb2[0]
Y2[0]
Cr2[0]
Y3[0]
Table 10. RGB 8-bit Multiplexed Mode (24-bit Color)
IDF#
Format
6
RGB 8-bit
Pixel#
P0a
P0b
P0c
P1a
P1b
P1c
P2a
P2b
P2c
Bus Data
D[7]
B0[7]
G0[7]
R0[7]
B1[7]
G1[7]
R1[7]
B2[7]
G2[7]
R2(7)
D[6]
B0[6]
G0[6]
R0[6]
B1[6]
G1[6]
R1[6]
B2[6]
G2[6]
R2(6)
D[5]
B0[5]
G0[5]
R0[5]
B1[5]
G1[5]
R1[5]
B2[5]
G2[5]
R2(5)
D[4]
B0[4]
G0[4]
R0[4]
B1[4]
G1[4]
R1[4]
B2[4]
G2[4]
R2(4)
D[3]
B0[3]
G0[3]
R0[3]
B1[3]
G1[3]
R1[3]
B2[3]
G2[3]
R2(3)
D[2]
B0[2]
G0[2]
R0[2]
B1[2]
G1[2]
R1[2]
B2[2]
G2[2]
R2(2)
D[1]
B0[1]
G0[1]
R0[1]
B1[1]
G1[1]
R1[1]
B2[1]
G2[1]
R2(1)
D[0]
B0[0]
G0[0]
R0[0]
B1[0]
G1[0]
R1[0]
B2[0]
G2[0]
R2(0)
t
HSW
Pixel
Data
POut/
XCLK
HSYNC
t
HD
P0a
P0b
P0c
P1a
P1b
P1c
t
PH3
t
P3
t
HP3
t
SP3
D[7:0]
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