8
Am79Q4457/5457 Data Sheet
PIN DESCRIPTIONS
Pin Name
Type
Description
A/µ
Input
A-law or µ-law Select. The A-law/µ-law select pin is used to inform the QSLAC-NP device which
compression/expansion standard to use. A logic Low signal (0 V) on the A-law/µ-law pin selects
the µ-law standard, and a logic High (+5 V) selects the A-law standard. The A-law/µ-law input can
be connected to V
CCD directly, eliminating the need for a external pull-up resistor. Therefore, the
device can be programmed for A-law by connecting the A/µ input to V
CCD and can be programmed
for µ-law by connecting the device pin to DGND.
CCLK
Input
(Am79Q4457 Device Only) Control Clock. The Control Clock input shifts data into and out of the
Serial Interface of the QSLAC-NP device. The maximum clock rate is 4.096 MHz. (Serial control
on the Am79Q4457 device only.)
CI
Input
(Am79Q4457 Device Only) Control Data. Control Data is written into the selected Channel Control
Register (see CS
N) via the CI pin. The data is shifted in the Most Significant Bit (MSB) first. The
data rate is determined by CCLK. (Serial control on the Am79Q4457 device only.)
CO
Output
(Am79Q4457 Device Only) Control Data. Control Data is read in serial form from the Enabled
Channel Register (see CS
N) via the CO pin. Data is shifted out with the MSB first. The data rate is
determined by the Control Clock (CCLK). (Serial control available on the Am79Q4457 device only.)
CS
1, CS2,
CS
3, CS4
Input
(Am79Q4457 Device Only) Chip Select. The Chip Select (CS
N) input (active Low) enables
Channel N of the device so that control data can be written to or read from the channel. CS
1
enables Channel 1, CS
2 enables Channel 2, CS3 enables Channel 3, and CS4 enables Channel
4. (Serial control on the Am79Q4457 device only.)
DRA
Input
PCM. The PCM data for Channels 1, 2, 3, and 4 is serially received on the DRA port during the time
slot determined by the Receive Frame Sync Signal (FSR
N). Data is always received with the MSB
first. A byte of data for each channel is received every 125 µs at the PCLK rate.
DXA
Output
PCM. The transmit data from Channels 1, 2, 3, and 4 is sent serially out the DXA port during
time slots determined by the Transmit Frame Sync (FSX
N) signal for that channel. Data is always
transmitted with the MSB first. The output is available every 125 µs and the data is shifted out
in 8-bit bursts at the PCLK rate. DXA is high impedance between time slots.
FSR
1, FSR2,
FSR
3, FSR4
Input
Receive Frame Sync. The Receive Frame Sync pulse for Channel N is an 8 kHz signal that
identifies the receive time slot for Channel N on a system’s receive PCM frame. The QSLAC-
NP device references channel time slots with respect to this input, which must be
synchronized to PCLK. There are both Long-Frame Sync and Short-Frame Sync modes
available on the QSLAC-NP device.
FSX
1, FSX2,
FSX
3, FSX4
Input
Transmit Frame Sync. The Transmit Frame Sync pulse for Channel N is an 8 kHz signal that
identifies the transmit time slot for Channel N during the system’s transmit PCM frame. The
QSLAC-NP device references individual channel time slots with respect to this input, which
must be synchronized to PCLK. There are both Long Frame Sync and Short Frame Sync
modes available on the QSLAC-NP device.
I1
IN1, I2IN1,
I1
IN2, I2IN2,
I1
IN3, I2IN3,
I1
IN4, I2IN4
Current
(I2
IN on Am79Q4457 Device Only) Analog Inputs. The analog voice band voltage signal is applied
to the I
IN input of the QSLAC-NP device through a resistor. The IIN input is a virtual AC ground input
(summing node). I
IN is biased at the voltage on the VREF1 pin. The audio signal is sampled, digitally
processed and encoded, and then made available at the TTL-compatible PCM output (DXA).
There are two inputs per channel in the 44-pin QSLAC-NP device. I1
IN1 is input 1 of Channel 1 and
I2
IN1 is input 2 of Channel 1; I1IN2 and I2IN2 are inputs 1 and 2 of Channel 2; I1IN3 and I2IN3 are inputs
1 and 2 of Channel 3; and I1
IN4 and I2IN4 are inputs 1 and 2 of Channel 4. See Figure 9 for more
details.
I
REF1, IREF2,
I
REF3
Output
(I
REF2 and IREF3 on Am79Q4457 Device Only). Reference Current. The IREF outputs are biased at the
internal reference voltage, which is the same as the voltage on the V
REF1 pin. A resistor placed from
I
REFn (n = 1, 2, or 3) to ground sets one of three reference currents used by the Analog-to-Digital (A-
to-D) converter to encode the signal current present on Iy
INn (n = channel number [1 to 4] and y =
input number [1 or 2]) into digital form. By setting different levels for I
REFx, three different
transmit gains can be achieved. The reference current used by a channel A-to-D is determined
by the Transmit Gain Select (TGS) bits in the channel control register. The absolute transmit gain
is determined by the reference current selected and the input resistance connected to I
IN. See
Figure 9 and Table 2 for more details.