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UPD30181 Datasheet(PDF) 6 Page - NEC |
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UPD30181 Datasheet(HTML) 6 Page - NEC |
6 / 444 page User’s Manual U14272EJ3V0UM 6 Major Revisions in This Edition (1/5) Page Description Throughout this manual Separation of the following parts of the previous (the 2nd) edition CHAPTER 3 MIPS III INSTRUCTION SET SUMMARY, CHAPTER 4 MIPS16 INSTRUCTION SET, CHAPTER 5 VR4181 PIPELINE, CHAPTER 6 MEMORY MANAGEMENT SYSTEM (first half), CHAPTER 7 EXCEPTION PROCESSING (second half), CHAPTER 9 CACHE MEMORY, CHAPTER 10 CPU CORE INTERRUPTS, CHAPTER 27 MIPS III INSTRUCTION SET DETAILS, CHAPTER 28 MIPS16 INSTRUCTION SET FORMAT p. 30 Deletion of modem block in Figure 1-1. Internal Block Diagram p. 34 Modification of description in 1.3.16 LCD interface p. 35 Modification of Remark in 1.3.17 Wake-up events pp. 38 to 42 Addition of 1.4.2 CPU instruction set overview and 1.4.3 Data formats and addressing p. 43 Modification of description and deletion of figure in 1.4.4 CP0 registers pp. 45, 46 Addition of 1.4.9 Power modes and 1.4.10 Code compatibility p. 47 Addition of descriptions in 1.5 Clock Interface pp. 48, 49 Addition of Figure 1-8. External Circuits of Clock Oscillator and Figure 1-9. Incorrect Connection Circuits of Resonator p. 52 Modification of Note in 2.2.1 System bus interface signals p. 53 Modification of descriptions for SYSDIR and SYSEN# and addition of description in Note in 2.2.1 System bus interface signals p. 58 Addition of description for IRDIN/RxD2 in 2.2.10 IrDA interface signals p. 60 Addition and modification in 2.3 Pin Status in Specific Status pp. 63 to 66 Addition of 2.4 Recommended Connection of Unused Pins and I/O Circuit Types and 2.5 Pin I/O Circuits pp. 67 to 90 Addition of CHAPTER 3 CP0 REGISTERS p. 95 Modification of Table 4-6. DRAM Address Map p. 97 Modification of description in 5.1.1 RTC reset pp. 97 to 101, 104, 105 Addition of description in Note in Figure 5-1 through Figure 5-5, Figure 5-8, and Figure 5-9 p. 98 Modification in Figure 5-2. RSTSW Reset p. 101 Modification of description in 5.1.5 HALTimer shutdown p. 104 Addition of description in 5.3.1 Cold Reset p. 105 Modification of description in 5.3.2 Soft Reset pp. 106, 107 Addition of 5.4 Notes on Initialization p. 108 Modification in Figure 6-1. VR4181 Internal Bus Structure p. 109 Modification of description in 6.1.2 (3) LCD module (LCD Control Unit) p. 111 Modification of description for bit 4 and addition of Caution and Remark in 6.2.1 BCUCNTREG1 (0x0A00 0000) p. 113 Modification of descriptions for bits 14 to 12, bits 3 to 0, and Remark in 6.2.3 BCUSPEEDREG (0x0A00 000C) p. 114 Modification of Figure 6-2. ROM Read Cycle and Access Parameters p. 117 Deletion of description for Div4 mode and addition of description in Remark in 6.2.6 (2) Peripheral clock (TClock) |
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