128Mx72 bits

DDR2 SDRAM Registered DIMM

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2 / July 2004

2

HYMP512R72(L)4

DESCRIPTION

Hynix HYMP512R72(L)4 series is registered 240-pin double data rate 2 Synchronous DRAM Dual In-Line Memory

Modules(DIMMs) which are organized as 128Mx72 high-speed memory arrays. Hynix HYMP512R72(L)4 series con-

sists of eighteen 128Mx4 DDR2 SDRAMs in 60-Lead FBGA chipsize packages. Hynix HYMP512R72(L)4 series pro-

vide a high performance 8-byte interface in 133.35mm width form factor of industry stanard. It is suitable for easy

interchange and addition. Hynix HYMP512R72(L)4 series is designed for high speed of up to 333MHz and offers fully

synchronous operations referenced to both rising and falling edges of differential clock inputs. While all addresses and

control inputs are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sam-

pled on both rising and falling edges of it. The data paths are internally pipelined and 4-bit prefetched to achieve very

high bandwidth. All input and output voltage levels are compatible with SSTL_1.8. High speed frequencies, program-

mable latencies and burst lengths allow variety of device operation in high performance memory system.

Hynix HYMP512R72(L)4 series incorporates SPD(serial presence detect). Serial presence detect function is imple-

mented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

ORDERING INFORMATION

Type

Part No.

Description

CL-tRCD-tRP

Form Factor

PC2-3200 (DDR2-400)

HYMP512R72(L)4-E4

one rank 1GB

Reg. DIMM

4-4-4

240pin Registered DIMM

133.35 mm x 30,00 mm

(MO-237)

HYMP512R72(L)4-E3

3-3-3

PC2-4300 (DDR2-533)

HYMP512R72(L)4-C5

5-5-5

HYMP512R72(L)4-C4

4-4-4

PC2-5300 (DDR2-667)

HYMP512R72(L)4-Y6

6-6-6

HYMP512R72(L)4-Y5

5-5-5

•

1GB (128M x 72) Registered DDR2 DIMM based on

128Mx4 DDR2 SDRAMs

•

JEDEC standard Double Data Rate2 Synchronous

DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power

Supply

•

JEDEC Standard 240-pin dual in-line memory mod-

ule (DIMM)

•

Error Check Correction (ECC) Capability

•

All inputs and outputs are compatible with SSTL_1.8

interface

•

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

•

Fully differential clock operations (CK & /CK)

•

Programmable CAS Latency 3 / 4 /5 supported

•

Programmable Burst Length 4 / 8 with both sequen-

tial and interleave mode

•

All inputs and outputs SSTL_1.8 compatible

•

Auto refresh and self refresh supported

•

•

Serial Presence Detect(SPD) with EEPROM

•

DDR2 SDRAM Package: 60ball FBGA