Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

DS90CR482 Datasheet(PDF) 6 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor. Click here to check the latest version.
Part # DS90CR482
Description  48-Bit LVDS Channel Link SER/DES 65 - 112 MHz
Download  21 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DS90CR482 Datasheet(HTML) 6 Page - National Semiconductor (TI)

Back Button DS90CR482 Datasheet HTML 2Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 3Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 4Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 5Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 6Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 7Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 8Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 9Page - National Semiconductor (TI) DS90CR482 Datasheet HTML 10Page - National Semiconductor (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 21 page
background image
Chipset RSKM Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(Notes 4, 7). See Applications Infor-
mation section for more details on this parameter and how to apply it.
Symbol
Parameter
Min
Typ
Max
Units
RSKM
Receiver Skew Margin without
Deskew in non-DC Balance Mode,
(Figure 13), (Note 5)
f = 112 MHz
170
ps
f = 100 MHz
170
240
ps
f = 85MHz
300
350
ps
f = 66MHz
300
350
ps
RSKM
Receiver Skew Margin without
Deskew in DC Balance Mode,
(Figure 13), (Note 5)
f = 112 MHz
170
ps
f = 100 MHz
170
200
ps
f = 85 MHz
250
300
ps
f = 66 MHz
250
300
ps
RSKMD
Receiver Skew Margin with Deskew
in DC Balance, (Figure 14),
(Note 6)
f=33to80
MHz
0.25TBIT
ps
RDR
Receiver Deskew Range
f = 80 MHz
± 1
TBIT
RDSS
Receiver Deskew Step Size
f = 80 MHz
0.3 TBIT
ns
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VTH,VTL,VOD and ∆VOD).
Note 4: The Minimum and Maximum Limits are based on statistical analysis of the device performance over voltage and temperature ranges. This parameter is
functionally tested on Automatic Test Equipment (ATE). ATE is limited to 85MHz. A sample of characterization parts have been bench tested to verify functional
performance.
Note 5: Receiver Skew Margin (RSKM) is defined as the valid data sampling region at the receiver inputs. This margin takes into account transmitter output pulse
positions (min and max) and the receiver input setup and hold time (internal data sampling window, RSPOS). This margin allows for LVDS interconnect skew,
inter-symbol interference (both dependent on type/length of cable) and clock jitter (TJCC).
RSKM
≥ cable skew (type, length) + source clock jitter (cycle to cycle,TJCC) + ISI (if any). See Applications Information section for more details.
Note 6: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain the
receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).
RSKMD
≥ ISI + TPPOS(variance) + source clock jitter (cycle to cycle, TJCC). See Applications Information section for more details.
Note 7: Typical values for RSKM and RSKMD are applicable for fixed VCC and T A of the Transmitter and Receiver (both are assumed to be at the same VCC and
T A points).
www.national.com
6


Similar Part No. - DS90CR482

ManufacturerPart #DatasheetDescription
logo
National Semiconductor ...
DS90CR482 NSC-DS90CR482 Datasheet
899Kb / 21P
   48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz
logo
Texas Instruments
DS90CR482 TI1-DS90CR482 Datasheet
1Mb / 25P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz
logo
National Semiconductor ...
DS90CR482VS NSC-DS90CR482VS Datasheet
899Kb / 21P
   48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz
logo
Texas Instruments
DS90CR482VS/NOPB TI1-DS90CR482VS/NOPB Datasheet
1Mb / 25P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz
DS90CR482VSX/NOPB TI1-DS90CR482VSX/NOPB Datasheet
1Mb / 25P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz
More results

Similar Description - DS90CR482

ManufacturerPart #DatasheetDescription
logo
National Semiconductor ...
DS90CR481 NSC-DS90CR481_06 Datasheet
899Kb / 21P
   48-Bit LVDS Channel Link SER/DES − 65 - 112 MHz
logo
Texas Instruments
DS90CR481 TI1-DS90CR481_15 Datasheet
1Mb / 25P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES ??65 - 112 MHz
DS90CR483 TI1-DS90CR483_15 Datasheet
1Mb / 27P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
logo
National Semiconductor ...
DS90CR483 NSC-DS90CR483_04 Datasheet
489Kb / 22P
   48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
logo
Texas Instruments
DS90CR483A TI1-DS90CR483A_15 Datasheet
1Mb / 27P
[Old version datasheet]   48-Bit LVDS Channel Link SER/DES - 33 - 112 MHz
DS90CR483A TI1-DS90CR483A Datasheet
402Kb / 26P
[Old version datasheet]   DS90CR483A/DS90CR484A 48-Bit LVDS Channel Link SER/DES 33-112 MHz
DS90UB913Q TI1-DS90UB913Q Datasheet
182Kb / 5P
[Old version datasheet]   10-100MHz 10/12-Bit FPD-Link III SER/DES
logo
National Semiconductor ...
DS92LV3241 NSC-DS92LV3241_10 Datasheet
171Kb / 6P
   Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des
DS90CR483 NSC-DS90CR483 Datasheet
348Kb / 17P
   48-Bit LVDS Channel Link Serializer/Deserializer
DS90CF384A NSC-DS90CF384A Datasheet
784Kb / 16P
   3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz, 3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link-65 MHz
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com