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TMP470R1B768PGE Datasheet(PDF) 11 Page - Texas Instruments |
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TMP470R1B768PGE Datasheet(HTML) 11 Page - Texas Instruments |
11 / 46 page www.ti.com TMS470R1B768 16/32-Bit RISC Flash Microcontroller SPNS108 – AUGUST 2005 Table 2. Terminal Functions (continued) TERMINAL INTERNAL TYPE(1)(2) PULLUP/ DESCRIPTION NAME NO. PULLDOWN(3) TEST/DEBUG (T/D) (CONTINUED) Test enable. Reserved for internal use only. TI recommends that this pin be TEST 38 3.3-V I IPD (20 µA) connected to ground or pulled down to ground by an external resistor. Serial input for controlling the state of the CPU test access port (TAP) TMS 120 3.3-V I IPU (20 µA) controller (JTAG) Serial input for controlling the second TAP. TI recommends that this pin be TMS2 121 3.3-V I IPU (20 µA) connected to VCCIO or pulled up to VCCIO by an external resistor. Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG) TRST 37 3.3-V I IPD (20 µA) Boundary-Scan Logic. TI recommends that this pin be pulled down to ground by an external resistor. FLASH Flash test pad 1. For proper operation, this pin must not be connected FLTP1 134 NC [no connect (NC)]. Flash test pad 2. For proper operation, this pin must not be connected FLTP2 133 NC [no connect (NC)]. Flash external pump voltage (3.3 V). This pin is required for both flash read VCCP 135 3.3-V PWR and flash program and erase operations. SUPPLY VOLTAGE CORE (1.8 V) 14 31 55 VCC 86 1.8-V PWR Core logic supply voltage 93 128 132 SUPPLY VOLTAGE DIGITAL I/O (3.3 V) 17 VCCIO 53 3.3-V PWR Digital I/O supply voltage 82 SUPPLY GROUND CORE 11 30 54 85 VSS GND Core supply ground reference 92 127 131 136 SUPPLY GROUND DIGITAL I/O 16 VSSIO 52 GND Digital I/O supply ground reference 81 11 |
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