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MCP3302 Datasheet(PDF) 5 Page - Microchip Technology |
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MCP3302 Datasheet(HTML) 5 Page - Microchip Technology |
5 / 40 page 2002 Microchip Technology Inc. DS21697B-page 5 MCP3302/04 Timing Specifications: Clock Frequency (Note 8) FCLK 0.105 0.105 — — 2.1 1.05 MHz MHz VDD = 5V, FSAMPLE = 100 ksps VDD = 2.7V, FSAMPLE = 50 ksps Clock High Time THI 210 — — ns Note 5 Clock Low Time TLO 210 — — ns Note 5 CS Fall To First Rising CLK Edge TSUCS 100 — — ns Data In Setup time TSU 50 — — ns Data In Hold Time THD —— 50 ns CLK Fall To Output Data Valid TDO —— 125 200 ns ns VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 CLK Fall To Output Enable TEN —— 125 200 ns ns VDD = 5V, see Figure 3-1 VDD = 2.7V, see Figure 3-1 CS Rise To Output Disable TDIS — — 100 ns See test circuits, Figure 3-1 Note 1 CS Disable Time TCSH 475 — — ns DOUT Rise Time TR — — 100 ns See test circuits, Figure 3-1 Note 1 DOUT Fall Time TF — — 100 ns See test circuits, Figure 3-1 Note 1 Power Requirements: Operating Voltage VDD 2.7 — 5.5 V Operating Current IDD — — 300 200 450 — µAVDD, VREF = 5V, DOUT unloaded VDD, VREF = 2.7V, DOUT unloaded Standby Current IDDS —0.05 1 µACS = VDD = 5.0V Temperature Ranges: Specified Temperature Range TA -40 — +85 °C Operating Temperature Range TA -40 — +85 °C Storage Temperature Range TA -65 — +150 °C Thermal Package Resistance: Thermal Resistance, 14L-PDIP θJA —70 — °C/W Thermal Resistance, 14L-SOIC θJA —108 — °C/W Thermal Resistance, 14L-TSSOP θJA —100 — °C/W Thermal Resistance, 16L-PDIP θJA —70 — °C/W Thermal Resistance, 16L-SOIC θJA —90 — °C/W ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Symbol Min Typ Max Units Conditions Note 1: This specification is established by characterization and not 100% tested. 2: See characterization graphs that relate converter performance to VREF level. 3: VIN = 0.1V to 4.9V @ 1 kHz. 4: VDD =5VP-P ±500 mV @ 1 kHz, see test circuit Figure 3-3. 5: Maximum clock frequency specification must be met. 6: VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz 7: TSSOP devices are only specified at 25°C and +85°C. 8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency. |
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