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UPD70F3116GJ-UEN-A Datasheet(PDF) 9 Page - NEC |
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UPD70F3116GJ-UEN-A Datasheet(HTML) 9 Page - NEC |
9 / 826 page 9 User’s Manual U14492EJ5V0UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................18 1.1 Outline........................................................................................................................................ 18 1.2 Features ..................................................................................................................................... 21 1.3 Applications............................................................................................................................... 23 1.4 Ordering Information ................................................................................................................ 23 1.5 Pin Configuration (Top View)................................................................................................... 24 1.6 Configuration of Function Block ............................................................................................. 26 1.6.1 Internal block diagram ..................................................................................................................26 1.6.2 Internal units.................................................................................................................................27 1.7 Differences Between Products ................................................................................................ 29 CHAPTER 2 PIN FUNCTIONS ................................................................................................................30 2.1 List of Pin Functions ................................................................................................................ 30 2.2 Pin Status................................................................................................................................... 36 2.3 Description of Pin Functions ................................................................................................... 37 2.4 Types of Pin I/O Circuit and Connection of Unused Pins..................................................... 45 2.5 Pin I/O Circuits .......................................................................................................................... 47 CHAPTER 3 CPU FUNCTION.................................................................................................................48 3.1 Features ..................................................................................................................................... 48 3.2 CPU Register Set ...................................................................................................................... 49 3.2.1 Program register set.....................................................................................................................50 3.2.2 System register set.......................................................................................................................51 3.3 Operation Modes....................................................................................................................... 57 3.3.1 Operation modes..........................................................................................................................57 3.3.2 Operation mode specification .......................................................................................................58 3.4 Address Space .......................................................................................................................... 59 3.4.1 CPU address space .....................................................................................................................59 3.4.2 Image ...........................................................................................................................................60 3.4.3 Wrap-around of CPU address space............................................................................................61 3.4.4 Memory map ................................................................................................................................62 3.4.5 Area..............................................................................................................................................63 3.4.6 External memory expansion .........................................................................................................67 3.4.7 Recommended use of address space ..........................................................................................68 3.4.8 On-chip peripheral I/O registers ...................................................................................................70 3.4.9 Programmable peripheral I/O registers ........................................................................................81 3.4.10 Specific registers ..........................................................................................................................98 3.4.11 System wait control register (VSWC) ...........................................................................................98 3.4.12 Cautions .......................................................................................................................................98 CHAPTER 4 BUS CONTROL FUNCTION...........................................................................................100 4.1 Features ................................................................................................................................... 100 4.2 Bus Control Pins ..................................................................................................................... 100 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access.....................100 4.3 Memory Block Function ......................................................................................................... 101 |
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