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UPD703114GF-XXX-3BA Datasheet(PDF) 9 Page - NEC |
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UPD703114GF-XXX-3BA Datasheet(HTML) 9 Page - NEC |
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9 / 692 page  9 User’s Manual U15195EJ5V0UD CONTENTS CHAPTER 1 INTRODUCTION .................................................................................................................17 1.1 Outline........................................................................................................................................ 17 1.2 Features ..................................................................................................................................... 19 1.3 Applications............................................................................................................................... 21 1.4 Ordering Information ................................................................................................................ 21 1.5 Pin Configuration (Top View)................................................................................................... 22 1.6 Configuration of Function Block ............................................................................................. 25 1.6.1 Internal block diagram ..................................................................................................................25 1.6.2 Internal units.................................................................................................................................26 CHAPTER 2 PIN FUNCTIONS ................................................................................................................28 2.1 List of Pin Functions ................................................................................................................ 28 2.2 Pin Status................................................................................................................................... 33 2.3 Description of Pin Functions ................................................................................................... 34 2.4 Types of Pin I/O Circuits and Connection of Unused Pins................................................... 43 2.5 Pin I/O Circuits .......................................................................................................................... 45 CHAPTER 3 CPU FUNCTION.................................................................................................................46 3.1 Features ..................................................................................................................................... 46 3.2 CPU Register Set ...................................................................................................................... 47 3.2.1 Program register set.....................................................................................................................48 3.2.2 System register set.......................................................................................................................49 3.3 Operation Modes....................................................................................................................... 55 3.3.1 Operation modes..........................................................................................................................55 3.3.2 Operation mode specification .......................................................................................................56 3.4 Address Space .......................................................................................................................... 57 3.4.1 CPU address space .....................................................................................................................57 3.4.2 Image ...........................................................................................................................................58 3.4.3 Wrap-around of CPU address space............................................................................................59 3.4.4 Memory map ................................................................................................................................60 3.4.5 Area..............................................................................................................................................61 3.4.6 External memory expansion .........................................................................................................65 3.4.7 Recommended use of address space ..........................................................................................66 3.4.8 On-chip peripheral I/O registers ...................................................................................................68 3.4.9 Specific registers ..........................................................................................................................78 3.4.10 System wait control register (VSWC) ...........................................................................................78 3.4.11 Cautions .......................................................................................................................................78 CHAPTER 4 BUS CONTROL FUNCTION.............................................................................................80 4.1 Features ..................................................................................................................................... 80 4.2 Bus Control Pins ....................................................................................................................... 80 4.2.1 Pin status during internal ROM, internal RAM, and on-chip peripheral I/O access.......................80 4.3 Memory Block Function ...........................................................................................................81 |
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