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K7N161801-FI16 Datasheet(PDF) 11 Page - Samsung semiconductor |
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K7N161801-FI16 Datasheet(HTML) 11 Page - Samsung semiconductor |
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11 / 18 page  512Kx36 & 1Mx18 Flow-Through NtRAMTM - 11 - Rev 3.0 Nov. 2003 K7M161825A K7M163625A Output Load(B), (for tLZC, tLZOE, tHZOE & tHZC) Dout 353 Ω / 1538Ω 5pF* +3.3V for 3.3V I/O 319 Ω / 1667Ω Fig. 1 * Including Scope and Jig Capacitance Output Load(A) Dout Zo=50 Ω RL=50 Ω VL=1.5V for 3.3V I/O VDDQ/2 for 2.5V I/O /+2.5V for 2.5V I/O 30pF* AC TIMING CHARACTERISTICS(VDD=3.3V+0.165V/-0.165V, TA=0 °C to +70°C) Notes : 1. The above parameters are also guaranteed at industrial temperature range. 2. All address inputs must meet the specified setup and hold times for all rising clock(CLK) edges when ADV is sample d low and CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected. 3. Chip selects must be valid at each rising edge of CLK(when ADV is Low) to remain enabled. 4. A write cycle is defined by WE low having been registerd into the device at ADV Low, A Read cycle is defined by WE High with ADV Low, Both cases must meet setup and hold times. 5. To avoid bus contention, At a given vlotage and temperature tLZC is more than tHZC. The soecs as shown do not imply bus contention because tLZC is a Min. parameter that is worst case at totally different test conditions (0 °C,3.465V) than tHZC, which is a Max. parameter(worst case at 70°C,3.135V) It is not possible for two SRAMs on the same board to be at such different voltage and temperatue. PARAMETER SYMBOL -65 -75 UNIT MIN MAX MIN MAX Cycle Time tCYC 7.5 - 8.5 - ns Clock Access Time tCD - 6.5 - 7.5 ns Output Enable to Data Valid tOE - 3.5 - 3.5 ns Clock High to Output Low-Z tLZC 2.5 - 2.5 - ns Output Hold from Clock High tOH 2.5 - 2.5 - ns Output Enable Low to Output Low-Z tLZOE 0 - 0 - ns Output Enable High to Output High-Z tHZOE - 3.5 - 3.5 ns Clock High to Output High-Z tHZC - 3.8 - 4.0 ns Clock High Pulse Width tCH 2.5 - 2.8 - ns Clock Low Pulse Width tCL 2.5 - 2.8 - ns Address Setup to Clock High tAS 1.5 - 2.0 - ns CKE Setup to Clock High tCES 1.5 - 2.0 - ns Data Setup to Clock High tDS 1.5 - 2.0 - ns Write Setup to Clock High (WE, BWX) tWS 1.5 - 2.0 - ns Address Advance Setup to Clock High tADVS 1.5 - 2.0 - ns Chip Select Setup to Clock High tCSS 1.5 - 2.0 - ns Address Hold from Clock High tAH 0.5 - 0.5 - ns CKE Hold from Clock High tCEH 0.5 - 0.5 - ns Data Hold from Clock High tDH 0.5 - 0.5 - ns Write Hold from Clock High (WE , BW X) tWH 0.5 - 0.5 - ns Address Advance Hold from Clock High tADVH 0.5 - 0.5 - ns Chip Select Hold from Clock High tCSH 0.5 - 0.5 - ns ZZ High to Power Down tPDS 2 - 2 - cycle ZZ Low to Power Up tPUS 2 - 2 - cycle |
Similar Part No. - K7N161801-FI16 |
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Similar Description - K7N161801-FI16 |
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