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IDT72V3693L15PF Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT72V3693L15PF Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 30 page 10 COMMERCIALTEMPERATURERANGE IDT72V3683/72V3693/72V36103 3.3V CMOS SyncFIFOTM WITH BUS-MATCHING 16,384 x 36, 32,768 x 36 and 65,536 x 36 BIG-ENDIAN/FIRST WORD FALL THROUGH (BE/ FWFT) — ENDIAN SELECTION Thisisadualpurposepin. AtthetimeofReset,theBEselectfunctionisactive, permittingachoiceofBig-orLittle-Endianbytearrangementfordatareadfrom Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long word size, the Big-Endian function has no application and the BE input is a “don’t care”1.) A HIGH on the BE/ FWFTinputwhentheReset(RS1)inputgoesfromLOW toHIGHwillselectaBig-Endianarrangement. Inthiscase,themostsignificant byte (word) of the long word written to Port A will be read from Port B first; the least significant byte (word) of the long word written to Port A will be read from Port B last. A LOW on the BE/ FWFTinputwhentheReset(RS1)inputgoesfromLOW toHIGHwillselectaLittle-Endianarrangement. Inthiscase,theleastsignificant byte (word) of the long word written to Port A will be read from Port B first; the most significant byte (word) of the long word written to Port A will be read from Port B last. Refer to Figure 2 for an illustration of the BE function. See Figure 3 (Reset) for an Endian select timing diagram. — TIMING MODE SELECTION AfterReset,theFWFTselectfunctionisactive,permittingachoicebetween two possible timing modes: IDT Standard mode or First Word Fall Through (FWFT) mode. Once the Reset ( RS1)inputisHIGH,aHIGHontheBE/FWFT input during the next LOW-to-HIGH transition of CLKA and CLKB will select IDT Standard mode. This mode uses the Empty Flag function ( EF)toindicate whether or not there are any words present in the FIFO memory. It uses the FullFlagfunction( FF)toindicatewhetherornottheFIFOmemoryhasanyfree space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. Once the Reset ( RS1)inputisHIGH,aLOWontheBE/FWFT inputduring the next LOW-to-HIGH transition of CLKA and CLKB will select FWFT mode. ThismodeusestheOutputReadyfunction(OR)toindicatewhetherornotthere is valid data at the data outputs (B0-B35). It also uses the Input Ready function (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Reset, the level applied to the BE/ FWFT input to choose the desired timing mode must remain static throughout FIFO operation. Refer to Figure 3 (Reset) for a First Word Fall Through select timing diagram. PROGRAMMING THE ALMOST-EMPTY AND ALMOST-FULL FLAGS Two registers in the IDT72V3683/72V3693/72V36103 are used to hold the offsetvaluesfortheAlmost-EmptyandAlmost-Fullflags. TheAlmost-Emptyflag ( AE)OffsetregisterislabeledXandAlmost-Fullflag(AF)Offsetregisterislabeled Y. The offset registers can be loaded with preset values during the reset of the FIFO, programmed in parallel using the FIFO’s Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). FS2 FS0/ SD, and FS1/ SEN function the same way in both IDT Standard and FWFT modes. SIGNAL DESCRIPTION RESET ( RS1, RS2) After power up, a Reset operation must be performed by providing a LOW pulse to RS1 and RS2 simultaneously. Afterwards, the FIFO memory of the IDT72V3683/72V3693/72V36103 undergoes a complete reset by taking its Reset ( RS1andRS2)inputLOWforatleastfourPortAclock(CLKA)andfour Port B clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can switch asynchronously to the clocks. A Reset initializes the internal read and write pointers and forces the Full/Input Ready flag ( FF/IR)LOW,theEmpty/Output Ready flag ( EF/OR)LOW,theAlmost-Emptyflag(AE)LOW,andtheAlmost- Full flag ( AF)HIGH. AReset(RS1)alsoforcestheMailboxflag(MBF1)ofthe parallelmailboxregisterHIGH,andatthesametimethe RS2andMBF2operate likewise. After a Reset, the FIFO’s Full/Input Ready flag is set HIGH after two write clock cycles to begin normal operation. A LOW-to-HIGH transition on the FlFO Reset ( RS1)inputlatchesthevalue of the Big-Endian (BE) input for determining the order by which bytes are transferred through Port B. A LOW-to-HIGH transition on the FlFO Reset ( RS1) input also latches the values of the Flag Select (FS0, FS1 and FS2) inputs for choosing the Almost- FullandAlmost-Emptyoffsetprogrammingmethod(fordetailsseeTable1,Flag Programming, and Almost-Empty and Almost-Full flag offset programming section). The relevant Reset timing diagram can be found in Figure 3. PARTIAL RESET ( PRS) The FIFO memory of the IDT72V3683/72V3693/72V36103 undergoes a limited reset by taking its Partial Reset ( PRS)inputLOWforatleastfourPortA clock(CLKA)andfourPortBclock(CLKB)LOW-to-HIGHtransitions.TheRTM pin must be LOW during the time of Partial Reset. The Partial Reset input can switchasynchronouslytotheclocks. APartialResetinitializestheinternalread andwritepointersandforcestheFull/InputReadyflag( FF/IR)LOW,theEmpty/ Output Ready flag ( EF/OR) LOW, the Almost-Empty flag (AE) LOW, and the Almost-Fullflag( AF)HIGH. APartialResetalsoforcestheMailboxflag(MBF1, MBF2)oftheparallelmailboxregisterHIGH.AfteraPartialReset,theFIFO’s Full/Input Ready flag is set HIGH after two Write Clock cycles to begin normal operation. See Figure 4, Partial Reset (IDT Standard and FWFT Modes) for the relevant timing diagram. Whatever flag offsets, programming method (parallel or serial), and timing mode(FWFTorIDTStandardmode)arecurrentlyselectedatthetimeaPartial Reset is initiated, those settings will be remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Reset would be inconvenient. RETRANSMIT ( RT) The FIFO memory of these devices undergoes a Retransmit by taking its associatedRetransmit ( RT)inputLOWforatleastfourPortAClock(CLKA)and four Port B Clock (CLKB) LOW-to-HIGH transitions. The Retransmit initializes the read pointer of FIFO to the first memory location. The RTM pin must be HIGH during the time of Retransmit. Note that the RT inputismuxedwiththe PRSinput,thestateoftheRTMpindeterminingwhether this pin performs a Retransmit or a Partial Reset. See Figure 19 for Retransmit (Standard IDT mode) and figure 20 for Retransmit (FWFT mode) timing diagrams. NOTE: 1. Either a HIGH or LOW can be applied to a “don’t care” input with no change to the logical operation of the FIFO. Nevertheless, inputs that are temporarily “don’t care” (along with unused inputs) must not be left open, rather they must be either HIGH or LOW. |
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