V386

V386 Datasheet

9

5/25/05

Revision 2.0

Integrated Circuit Systems • 525 Race Street, San Jose, CA 95126 • tel (408) 297-1201 • www.icst.com

Figure 7. V386 LVDS Input Strobe Position

Figure 8. Receiver Input Skew Margin

Rspos0 Min

Previous Cycle

Rspos0 Max

Rspos1 Min

Rspos1 Max

Rspos2 Min

Rspos3 Min

Rspos2 Max

Rspos3 Max

Rspos4 Min

Rspos4 Max

Rspos5 Min

Rspos5 Max

Rspos6 Min

Rspos6 Max

Next Cycle

TCLK

Data

Clock

RCK+/RCK-

RX[n]+/RX[n]-

N = 0, 1, 2, 3

Skew Margin