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C9716J
100 MHz Clock Generator with SSCG and Power Management for Mobile Application
Preliminary
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
Rev. 1.0
4/28/2000
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
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Power Management Timing
Latency
Signal
Signal State
No. of rising edges of free
running PCI CLOCK (PCIF)
CS#
0 (disabled)
1
1 (enabled)
1
PD#
1 (cold start/normal operation)
3 mS
0 (power down)
1
NOTES:
1.
Clock on/off latency is defined in the number of rising edges of free running PCI CLOCK between the clock disable
goes low/high to the first valid clock comes out of the device.
Spectrum Spread Clocking
Spectrum Analysis
Spread
Non -Spread
Reduction